L波段四通道发射电路芯片的设计与实现

基于有源相控阵雷达的应用,设计了一款四通道的发射芯片,适用于发射1.2～1.4 GHz的射频信号.电路设计采用直接上变频的结构,将低频的基带信号转换为射频信号.针对直接上变频输出谐波多和输出功率低的问题,采用高阶滤波器、窄带选频网络的双平衡混频器和多级可调电压增益放大器(VGA)并联形式的驱动放大器等技术,降低了输出谐波的幅度并提高输出功率.电路采用SMIC 0.13 μm CMOS工艺进行了设计仿真和流片,芯片面积为3.6 mm×3.4 mm.测试结果表明,四通道直接上变频发射芯片的发射功率可达15.4 dBm,动态增益不小于36.3 dB,通道隔离度不小于43.3 dB.芯片的功耗为837.6 mW.     

应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器

这篇文章呈现了一个应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器,使用了改进的带负电容抵消技术Cherry-hooper放大器作为增益单元,采用了新颖的电路技术来实现增益调节,该技术在宽带PGA的设计中具有普适性,并且可以大大简化宽带PGA的设计。PGA通过两级增益单元和一级输出BUFFER的级联获得了最大增益30dB和远宽于3GHz的带宽。该PGA集成进整个60GHz无线收发机里面并且用TSMC65nm的CMOS工艺获得实现。整个接收机前端的测试结果表明接收机前端获得了18dB的可变增益范围和>3GHz的带宽,这证明提出的PGA本身获得了18dB的可变增益范围并且带宽是远大于3GHz的。该PGA电源电压为1.2V,功耗为10.7mW,核心版图面积仅仅为0.025mm^2。     

一种适用于IEEE802．15．4（ZigBee）标准的2．4GHz CMOS射频收发机设计

本文提出了一种适用于IEEE 802．15．4标准的2.4GHz免认证ISM频段的全集成CMOS射频收发机．接收机采用低中频结构以降低功耗、提高灵敏度,发射机则采用直接上变频结构以降低设计复杂度和功耗．芯片采用0.18μm 1P4M CMOS工艺以及MIM电容制造,供电电压1.8V ．测试结果显示,在误包率为1％时,接收机灵敏度达到了-97dBm ,发射机输出至100Ω差分天线端口的最大输出功率为＋3dBm ．接收模式和发射模式下的电流功耗分别为17mA和19mA ,芯片面积3.3mm ×2.8mm ．     

应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

OFDM超宽带3.1-4.8GHz CMOS射频收发机设计

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的CMOS射频收发机芯片的设计和实现。射频收发机采用零中频结构,主要模块包括：增益可控的宽带低噪声放大器、正交跨导复用下变频混频器、5阶Gm-C切比雪夫低通滤波器及可变增益放大器;采用多项滤波器进行边带杂散抑制的快速跳变频率综合器;宽带线性上变频正交调制器、片内有源双转单电路及输出可变增益放大器。芯片测试结果表明,接收机最大能够获得68dB的电压增益,其中42dB为可变增益,增益步长为6dB;在三个子带内的噪声系数为5.5~8.8dB;带内IIP3和带外IIP3不低于-4dBm和9dBm;发射机能够提供-10.7~-3dBm的输出功率,7.7dB的增益可控;输出1dB压缩点不低于-7.7dBm;发射信号边带抑制为32.4dBc,载波泄漏抑制可达31.1dBc;频率综合器的快速跳边时间低于2.05nS。芯片采用Jazz 0.18μm射频CMOS工艺流片,包括ESD防护PAD在内芯片总面积为6.1mm2;在1.8V的电源电压下,整个芯片的工作电流为221mA (RX+TX+SYN+Buffers）。     

应用于智能驾驶的77GHz毫米波汽车雷达收发机芯片

针对未来智能驾驶和无人驾驶对毫米波传感器多模式、多场景感知需求,设计并实现了一种77GHz多模毫米波雷达收发机芯片。芯片采用65nm CMOS工艺,集成了3路雷达发射机和4路接收机、调频连续波（FMCW）波形发生器、模数转换器以及高速数据接口等电路。利用交叉耦合中和电容技术提升了CMOS工艺上毫米波低噪声放大器、毫米波片上功放等电路性能,采用两点调制锁相环技术提升了FMCW信号带宽和调制速率。收发机的发射功率、波形样式、接收增益和带宽等参数具有较好的可配置性,满足未来多模式、小型化和低成本汽车雷达传感器需求。芯片测试结果显示,在76～81GHz频率范围内,接收机实现50dB的增益控制,最小噪声系数11dB,FMCW信号调频带宽达4.2GHz,调制速率达233MHz/μs,线性度优于0.1%,－45～+125℃全温范围内发射机典型输出功率大于13dBm。     

基于802.11a协议的无线局域网低噪声放大器和改进的有源双平衡混频器

提出了采用0.18μm CMOS工艺,应用于802.11a协议的无线局域网接受机的低噪声放大器和改进的有源双平衡混频器的一些简单设计概念。通过在5.8 GHz上采用1.8 V供电所得到的仿真结果,低噪声放大器转换电压增益,输入反射系数,输出反射系数以及噪声系数分别为14.8 dB,-20.8 dB,-23.1 dB和1.38 dB。其功率损耗为26.3 mW。设计版图面积为0.9 mm×0.67 mm。混频器的射频频率,本振频率和中频频率分别为5.8 GHz,4.6 GHz和1.2 GHz。在5.8 GHz上,混频器的传输增益,单边带噪声系数（SSB NF）,1 dB压缩点,输入3阶截点（IIP3）以及功率损耗分别为-2.4 dB,12.1 dB,3.68 dBm,12.78 dBm和22.3 mW。设计版图面积为1.4 mm×1.1 mm。     

基于微带无源电路的宽带毫米波分谐波混频器

设计了一款基于微带结构的宽带毫米波分谐波混频器。混频器中引入了短路结构的宽带射频滤波器以及一个高性能本振-中频双工器,这些无源电路能够抑制空闲组合频率,同时为中频、射频以及本振信号提供合适的回路。测试结果表明,本文设计的毫米波分谐波混频器射频工作频率为27~48 GHz,中频工作频率宽至6 GHz. 在整个工作频段内上、下变频损耗均小于12.5 dB。当射频为33 GHz,中频为1 GHz时,上变频、下变频达到最小变频损耗分别为8.2 dB和7.5 dB。     

基于0.18μm CMOS工艺的2.4/5.2GHz双频段LNA的设计

采用0.18 μm CMOS工艺,实现了双频段低噪声放大器设计.通过射频选择开关,电路可以分别工作在无线局域网标准802.11g规定的2.4 GHz和802.11a规定的5.2 GHz频段.该低噪声放大器为共源共栅结构,设计中采用了噪声阻抗和输入阻抗同时匹配的噪声优化技术.电路仿真结果表明:在2.4 GHz频段电路线性增益为15.4 dB,噪声系数为2.3 dB,1 dB压缩点为-12.5 dBm,IIP3为-4.7 dBm;5.2 GHz频段线性增益为12.5 dB,噪声系数为2.9 dB,1 dB压缩点为-11.3 dBm,IIP3为-5.5 dBm.     

应用于SC-UWB收发机的CMOS射频接收前端电路设计

设计了应用于单载波超宽带（SC-UWB）无线收发机中的CMOS射频接收前端电路. 该前端电路采用直接变频结构,包含一个差分低噪声放大器（LNA）、一个正交混频器和两个中频放大器。其中,LNA采用源级电感负反馈结构.首先给出了该类型LNA中输入匹配带宽关于栅源电容、工作频率及匹配目标值的表达式 然后考虑到栅极片上电感、键合电感及其精度,提出了在增益和功耗约束下的噪声因子优化策略。该LNA利用两级放大级的不同谐振点实现了7.1~8.1GHz频段上的平坦增益,并具有两种增益模式来改善接收机动态范围. 正交混频器采用折叠式双平衡吉尔伯特结构. 该射频前端电路采用TSMC0.18um RF CMOS工艺设计,芯片面积为1.43 mm2. 在高、低增益模式下,测得的最大转换增益分别为42dB和22dB,输入1dB压缩点为-40dBm和-20dBm,S11低于-18dB和-14.5dB,中频3dB带宽大于500MHz. 高增益模式下双边带噪声因子为4.7dB. 整个电路在1.8V供电电压下功耗为65mW。     

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3-5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is completely integrated in 0.13-mum standard CMOS technology. The receiver uses a feedback-based low-noise amplifier (LNA) to obtain an RF gain of 4 to 37 dB and an overall measured noise figure of 3.6 to 4.1 dB over the 3-5-GHz band of interest. The transmitter supports an error vector magnitude (EVM) of -28 dB up to -4 dBm output power and meets the FCC and WiMedia mask specifications. The power consumption from a single supply voltage of 1.5 V is 237 mW for the receiver and 284 mW for the transmitter, both including the synthesizer     

超宽带系统CMOS全集成射频收发器设计

本文介绍3.1-4.8GHz MB-OFDM系统的CMOS射频收发器。电路采用直接变频架构,由接收器、发射器和频率综合器组成。采用PGS隔离技术和其他隔离措施完成了单片射频收发器的版图布局。后仿真结果表明,接收链路可提供的最大增益为72dB,其52dB为可变增益,三个子频带内噪声系数介于5.2-7.8dB,带外IIP3不低于-3.4dBm。发射链路可提供的可控输出功率-8dBm到-2dBm,输出1dB压缩点不低于4dBm,输出信号边带抑制约44dBc,载波抑制不低于34dBc。频率综合器在三个频点间的跳变时间小于9ns。芯片采用Jazz0.18μm射频CMOS工艺设计,面积为6.1mm2。在1.8V电源电压下,总电流约221mA。     

A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process

This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 ^deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.     

An ultra-low-power RF transceiver for WBANs in medical applications

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks(WBANs)in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver(RX)with an ultra-low-power free-running ring oscillator and a high speed main transmitter(TX)with fast lock-in PLL.A passive wake-up receiver(WuRx)for wake-up function with a high power conversion efficiency(PCE)CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm~2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications

This paper describes a high-performance WLAN 802.11a/b/g radio transceiver, optimized for low-power in mobile applications, and for co-existence with cellular and Bluetooth systems in the same terminal. The direct-conversion transceiver architecture is optimized in each mode for low-power operation without compromising the challenging RF performance targets. A key transceiver requirement is a sensitivity of -77 dBm (at the LNA input) in 54 Mb/s OFDM mode while in the presence of a GSM1900 transmitter interferer. The receiver chain achieves an overall noise figure of 2.8/3.2 dB, consuming 168/185 mW at 2.8 V for the 2.4/5GHz bands, respectively. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate the transmitter LO leakage and the transceiver I/Q imbalances. Fabricated in a 70 GHz f/sub T/ 0.25-/spl mu/m SiGe BiCMOS technology for system-in-package (SiP) use, the dual-band, tri-mode transceiver occupies only 4.6 mm/sup 2/.     

Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Radar and Millimeter-Wave Imaging

This paper presents the first single-chip direct-conversion 77-85 GHz transceiver fabricated in SiGe HBT technology, intended for Doppler radar and millimeter-wave imaging, particularly within the automotive radar band of 77-81 GHz. A 1.3 mm times 0.9 mm 86-96 GHz receiver is also presented. The transceiver, fabricated in a 130 nm SiGe HBT technology with f_T/f_MAX of 230/300 GHz, consumes 780 mW, and occupies 1.3 mm times 0.9 mm of die area. Furthermore, it achieves 40 dB conversion gain in the receiver at 82 GHz, a 3 dB bandwidth extending from 77 to 85 GHz at 25degC, and covering the entire 77-81 GHz band up to 100degC, record 3.85 dB DSB noise figure measured at 82 GHz LO and 1 GHz IF, and an IP_1dB of -35 dBm. The transmitter provides + 11.5 dBm of saturated output power at 77 GHz, and a divide64 static frequency divider is included on-die. Successful detection of a Doppler shift of 30 Hz at a range of 6 m is shown. The 86-96 GHz receiver achieves 31 dB conversion gain, a 3 dB bandwidth of 10 GHz, and 5.2 dB DSB noise figure at 96 GHz LO and 1 GHz IF, and -99 dBc/Hz phase noise at 1 MHz offset. System-level layout and integration techniques that address the challenges of low-voltage transceiver implementation are also discussed.     

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode     

W波段集成化收发组件设计北大核心CSCD

基于混合微波集成电路技术(HMIC)设计了一种W波段小型化高频收发组件。该收发组件由固态发射机、环形器和接收机三部分组成。发射支路输入信号经过倍频放大后进入二选一开关,输出到天线自检口或经由环形器输出。为了实现高输出功率,该组件采用功率合成的设计思想,通过3 dB波导桥结构实现对两路功放的合成,解决了单个单片功率放大器的输出功率有限的问题。所设计的收发组件整体尺寸为125 mm×90 mm×26.5 mm。实测结果表明,在90~96 GHz工作频带范围内,遥测电压4.23 V。该收发组件的发射部分输出功率范围为33.6~35.4 dBm,开关隔离度大于110 dB;接收部分增益范围为30.2~33 dB,噪声系数小于6.5 dB。该组件具备良好的射频性能,同时实现了高集成度、大功率、高增益、高隔离度的要求。     

A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader

This paper describes a single-antenna low-power single-chip radio frequency identification (RFID) reader for mobile phone applications. The reader integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The direct conversion RF receiver architecture with the highly linear RF front-end circuit and DC offset cancellation circuit is used to give good immunity to the large transmitter leakage. It is suitable for a mobile phone reader with single-antenna architecture and low-power reader solution. The transmitter is implemented in the direct I/Q up-conversion architecture. The frequency synthesizer based on a fractional-N phase-locked-loop topology offering 900 MHz quadrature LO signals is also integrated with the RF transceiver. The reader is fabricated in a 0.18 mum CMOS technology, and its die size is 4.5 mm times 5.3 mm including electrostatic discharge I/O pads. The reader consumes a total current of 89 mA apart from the external power amplifier with 1.8 V supply voltage. It achieves an 8 dBm P1dB, an 18.5 dBm IIP3, and a maximum transmitter output power of 4 dBm.