损伤恢复机制对3D NAND闪存保持特性的影响

在3D NAND闪存的分布式编程擦除循环实验中发现,存储单元的保持特性随着编程擦除循环周期间隔的增加而改善。对实验数据的分析表明,编程擦除循环周期间隔中发生了损伤恢复,且在损伤恢复的两个机制中,氧化层电荷逸出对保持特性的改善起主要作用,而非界面陷阱修复。这说明,氧化层电荷逸出对于3D NAND闪存的保持特性有着重要影响。此外还发现,由于连续的电荷存储层所导致的电荷横向散布,损伤恢复对3D NAND闪存保持特性的影响与存储单元的编程模式有关。综上,损伤恢复机制是影响3D NAND闪存保持特性的一个重要因素,需要在产品的可靠性表征中予以考虑。     

基于NAND闪存的自适应闪存映射层设计

NAND闪存以非易失性、低功耗、抗辐射等优点,被广泛应用于嵌入式系统中.由于闪存写前需先擦写和高坏块率等硬件特性,成为其在应用中的障碍,需要通过闪存映射层进行存储管理.通过给出一种基于NAND型闪存的自适应闪存映射技术,对数据访问模式进行判断,为不同的访问模式提供不同粒度的地址映射方法,用于充分利用NAND闪存的优势克服其缺点,提高系统性能.该方法在Linux系统上予以实现,并进行了性能测试.     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

闪存容量随应用的扩展而增加

现在上市的各种系统产品, 几乎没有不包含闪存的。这些系统产品,由于以下原因而采用闪存。首先,需要利用闪存来存储BIOS,以及其它功能的程序;这些程序都是主处理器在执行各种任务时,必不可少的。其次,是需要利用闪存来储存数据;这时闪存的作用和硬盘类似。目前,闪存有两种类型──NAND型器件和NOR型器件。NAND型器件适合用于储存数据,而NOR型器件则适合存储程序。有些系统产品分别采用两种类型器件中的某一种,而许多系统产品则需要同时采用这两种类型的器件。例如PDA,它需要采用NOR闪存来存储操作系统,有了操作系统…     

新型多位非均匀沟道电荷俘获型存储器及新型虚拟源端的NAND阵列结构

为了解决传统多位存储NAND型存储器中位与位互相干扰的问题,本文提出了一种新型的用于多位存储的非均匀沟道电荷俘获型存储器及新型NAND结构。该器件能够很好地抑制SBE效应从而提供3比特/单元的存储能力。由于n-缓冲区的存在,由SBE效应导致的阈值电压漂移能够减小到400mV,在3比特/单元的存储能力下最小阈值电压窗口可以达到750mV。本器件还引入了富硅氮氧化硅层最为电荷俘获层,从而很好地提高了器件的电荷保持特性。     

SSD的现状及发展前景

半导体硬盘SSD(固态硬盘)由NAND闪存、NAND控制器以及用作缓冲存储器的DRAM所构成(见图1)。在SSD中,坏块管理、纠错编码(ECC)及单元调整等处理都由NAND控制器的闪存转换层(FTL)来执行。SSD的性能不仅取决于NAND闪存的性能,而且在很大程度上还会受到NAND控制器算法的影响。因此,在优化NAND控制器的设计时,需要考虑到NAND闪存的特性。本文将基于NAND闪存的器件技术及电路技术,以NAND控制器技术为中心,论述SSD技术的现状和今后的挑战等。     

开放式大容量NAND Flash数据存储系统设计与实现

完成了一种基于NAND Flash存储介质的开放武大容量数据存储系统设计,包括硬件系统以及软件系统的设计,并在软件设计中重点提出了应用于NAND闪存的数据管理算法,通过二级地址映射,按块中的脏页数回收脏块和按时间标记转移静态信息实现坏块管理,均匀损耗.该设计能为各种存储器件提供底层的NAND闪存存储系统,使其能方便快速地存储数据而不需要考虑NAND闪存的物理特性.     

应用决定闪存

目前从多芯片到复合组件的供应，快闪存储器分为不同的类型，关键是如何根据自己的需要选用适合的产品。一般地讲，存在NAND和NOR两种类型的闪存。前者用于数据存储应用，而NOR型快闪存储器用于代码存储。NAND器件的连续读取方式适合以数据块为基础的数据存储应用。便携设备是快闪存储器的最佳用武之地，尤其与旋转媒体相比更是如此(不考虑成本因素)。实际上，闪存比旋转媒体具有更小更轻的优势，从而构成便携式电子产品应用的两个关键要素。目前市场上呈现的一种发展趋势是设计师在寻求用NAND闪存代替NOR型器件，即使在代码存储应…     

一种适用于3D NAND闪存的分布式功率级LDO设计

由于3D NAND闪存芯片面积较大,其电源分布网络庞大、复杂,既需要满足多个块(block)并行读写时所需的600 mA峰值电流要求,也需要满足芯片在待机状态下的低功耗要求-针对以上问题,设计了一种为3D NAND闪存芯片进行供电的无片外电容的分布式功率级LDO电路.通过设计Active和Standby两种工作模式下的...     

闪存市场新格局

在过去的9个月里,闪存市场可谓翻天覆地的变化.受到消费电子产品持续需求的影响,一直苦苦追赶的NAND闪存终于在2005年第1季度盈利首次超过NOR闪存,此后一直保持优势至今.而就在此前不久,Apple爆料:新型的iPod将采用容量高达1GB的NAND闪存代替HDD.甚至,Apple很快将会采用4GB的NAND闪存代替同样容量的HDD,用于iPod迷你MP3播放器.一时之间,NAND闪存风生水起,而同属闪存一分子的NOR偃旗息鼓,有点风光不再.     

Improving the Retention and Endurance Characteristics of Charge-Trapping Memory by Using Double Quantum Barriers

We have studied the performance of double-quantum-barrier [TaN-Ir₃Si]-[HfAlO-LaAlO₃]-Hf_0.3N_0.2O_0.5-[HfAlO-SiO₂]-Si charge-trapping memory devices. These devices display good characteristics in terms of their plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degC. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.     

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current     

基于FPGA的智能分区存储系统设计

常规炮弹于恶劣环境下,内部信号采集处理系统存在意外瞬时掉电的情况。针对掉电情况下数据存储错误的问题,提出了一种基于FPGA的智能分区存储方法,在研究NAND Flash读写、擦除和存储的特点的基础上,设计了一种智能分区存储系统,实现了存储数据开始地址的智能检测及断电自动跳址开始下一次数据的续存。实弹试验证明,该系统提高了FLASH存储区域的利用率,有效的解决了数据存储系统在常规弹药制导化应用过程中的实际问题。     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

High‐Performance Top‐Gated Organic Field‐Effect Transistor Memory using Electrets for Monolithic Printed Flexible NAND Flash Memory

High‐performance top‐gated organic field‐effect transistor (OFET) memory devices using electrets and their applications to flexible printed organic NAND flash are reported. The OFETs based on an inkjet‐printed p‐type polymer semiconductor with efficiently chargeable dielectric poly(2‐vinylnaphthalene) (PVN) and high‐k blocking gate dielectric poly(vinylidenefluoride‐trifluoroethylene) (P(VDF‐TrFE)) shows excellent non‐volatile memory characteristics. The superior memory characteristics originate mainly from reversible charge trapping and detrapping in the PVN electret layer efficiently in low‐k/high‐k bilayered dielectrics. A strategy is devised for the successful development of monolithically inkjet‐printed flexible organic NAND flash memory through the proper selection of the polymer electrets (PVN or PS), where PVN/‐ and PS/P(VDF‐TrFE) devices are used as non‐volatile memory cells and ground‐ and bit‐line select transistors, respectively. Electrical simulations reveal that the flexible printed organic NAND flash can be possible to program, read, and erase all memory cells in the memory array repeatedly without affecting the non‐selected memory cells.     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

Perspective of flash memory realized on vertical Si nanowires

In this review article, the scaling challenges of planar non-volatile memory, especially the flash-types including both floating gate-based and charge-trap-based devices are firstly discussed. The promising prospects brought by 3-Dimensional (3-D) nano-wire-based cells have been presented along with various device demonstrations and discussions on vertical nano-wire platform. The memory devices with highly scaled single-crystal Si nanowire (SiNW) channel and a gate-all-around (GAA) structure achieve superior program/erase (P/E) speed, cycling and high-temperature retention characteristics as compared to the planar one and are considered as promising candidate for future ultra-high non-volatile flash memory application.     

Non-Volatile Memories for Removable Media

NAND Flash memory has become the preferred nonvolatile choice for portable consumer electronic devices. Features such as high density, low cost, and fast write times make NAND perfectly suited for media applications where large files of sequential data need to be loaded into the memory quickly and repeatedly. When compared to a hard disk drive, a limitation of the Flash memory is the finite number of erase/write cycles: most of commercially available NAND products are guaranteed to withstand 10$^{5}$ programming cycles at most. As a consequence, special care (remapping, bad block management algorithms, etc.) has to be taken when hard-drive based, read/write intensive applications, such as operating systems, are migrated to Flash-memory based devices. One of the basic requirements of the consumer market for data storage is the portability of stored data from one device to the other. Flash cards are the actual solution. A Flash card is a nonvolatile “system in package” in which a NAND Flash memory is embedded with a dedicated controller. This paper presents the basic features of the NAND Flash memory and the basic architecture of Flash cards. We provide an outlook on opportunities and challenges of future Flash systems.      

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond