面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6 4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.     

12位300MHz电流驱动型DAC

在电路误差、电路占用芯片面积相互折中和妥协的前提下提出了一种8+4结构的电流驱动型数模转换器.采用Q2 random walk方法设计了一个新型的双中心对称的电流矩阵,确保数模转换器的线性度.分析并求出了最佳电平交叉点,设计了电平钳位锁存器对开关电平限幅,DAC动态性能得到改善.在12位分辨率下,刷新率达到300MHz以上.     

12位400MS/s电流舵数模转换器

本文展示了一个12位400MS/s CMOS工艺的数模转换器。这款数模转换器采用6 2 4的分段结构和优化的开关方案来提升动态和静态性能。在400MS/s采样频率和10MHz输入信号频率的条件下,测试得到的无杂散动态范围达到77.18 dB。电路采用1.8V单电压供电,最大输出电流35mA。芯片采用标准1P-6M 0.18μm CMOS工艺制造,核心面积为0.6 mm2。     

一种用于数模转换器的电流-电压转换电路

介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。     

一种低功耗高速空间光调制器驱动电路

本文描述了一种新型的多量子阱空间光调制器驱动电路的设计和测试。为了解决时钟同步问题并减少功耗,我们有别于前人,将所有电路模块集成在一块芯片上。因为传统的单斜坡数模转换器无法消除电容的失配,所以我们转而采用64个列共享8位电阻串数模转换器来提供输出电压,实现0.5V至3.8V的可编程电压调控。这些数模转换器被紧密放置于6464 驱动阵列的上方力求减小失配。每个转换器消耗80uA电流,在280ns内完成一次转换。为了更快的传输速率,系统采用2级缓存,工作时钟50MHz,真刷新率达到50K帧每秒,整片功耗302mW。芯片采用0.35um CMOS工艺,面积5.5 mm7 mm。     

一种应用于14 bit 200 MS/s电流舵型DAC的数字校准技术

电流舵型数模转换器(DAC)广泛应用于通信系统。采用电流分叉结构的电流舵型DAC可以极大地减小电流源阵列的面积。提出一种可以应用于采用电流分叉结构的电流舵型DAC的数字校准技术。提出的后台校准技术可以同时消除高位电流源阵列和低位电流源阵列的失配误差。基于0.18μm CMOS工艺,设计并流片了一款14bit 200MS/s电流舵型DAC,经过数字校准后,无杂散动态范围(SFDR)能够提高至少24dB。在时钟频率为200MS/s,输出信号为2MHz时,SFDR能够达到80dB以上。芯片面积为1.26mm2,功耗为125mW。     

一种应用于14 bit 200 MS/s电流舵型DAC的数字校准技术北大核心CSCD

电流舵型数模转换器(DAC)广泛应用于通信系统。采用电流分叉结构的电流舵型DAC可以极大地减小电流源阵列的面积。提出一种可以应用于采用电流分叉结构的电流舵型DAC的数字校准技术。提出的后台校准技术可以同时消除高位电流源阵列和低位电流源阵列的失配误差。基于0.18μm CMOS工艺,设计并流片了一款14bit 200MS/s电流舵型DAC,经过数字校准后,无杂散动态范围(SFDR)能够提高至少24dB。在时钟频率为200MS/s,输出信号为2MHz时,SFDR能够达到80dB以上。芯片面积为1.26mm2,功耗为125mW。     

一种100dB输出动态范围的1.5bit功率数模转换器

介绍了一种1.5bit的双声道过采样数模转换器.它把过采样数模转换器和D类功率放大器这两部分集成在一起,不需要额外的低通滤波器即可直接驱动耳机扬声器等语音设备.它无需消耗直流功耗,对于常用的8Ω扬声器负载,其最大输出功率可达436mW,输出动态范围大于100dB.该电路采用TSMC 0.18μm工艺实现.芯片面积为0.28mm2,其中数字电路的电源电压为1.8V,D类功率放大器的电源电压为3.3V.     

一种100dB输出动态范围的1.5bit功率数模转换器

介绍了一种1.5bit的双声道过采样数模转换器.它把过采样数模转换器和D类功率放大器这两部分集成在一起,不需要额外的低通滤波器即可直接驱动耳机扬声器等语音设备.它无需消耗直流功耗,对于常用的8Ω扬声器负载,其最大输出功率可达436mW,输出动态范围大于100dB.该电路采用TSMC 0.18μm工艺实现.芯片面积为0.28mm2,其中数字电路的电源电压为1.8V,D类功率放大器的电源电压为3.3V.     

采用SAR结构的8通道12位ADC设计

本文设计实现了一个8通道12位逐次逼近型ADC。转换器内部集成了多路复用器、并/串转换寄存器和复合型DAC,实现了数字位的串行输出。整体电路采用HSPICE进行仿真,转换速率为133KSPS,转换时间为7.5μs。通过低功耗设计,工作电流降低为2.8mA。芯片基于0.6μmBiCMOS工艺完成版图设计,版图面积为2.5×2.2mm2。     

一种GSM无线发射系统中的低功耗数模转换器

针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源...     

A 10-bit 100 MSamples/s BiCMOS D/A Converter

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8µm BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of approximately 650mW. The area of the chip-core is 2.2mm × 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f _g0.1 f _s(f _s = 100MSamples/s) the measured SFDR is 50dB, and at f _g0.3 f _s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.     

A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.     

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 μm single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV·s and the settling time within ±0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm×1.2 mm (1.75 mm×0.7 mm for the DAC portion)     

A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

A dual 10-b/200-MSPS pipelined digital-to-analog converter (DAC) suitable for communication applications is here presented. Prior implementation limitations have been overcome through circuit techniques. A prototype has been designed using a 4-metal-levels 3.3-V 0.5-/spl mu/m BiCMOS technology and operates on a 3-phase clock synthesized by an on-chip delay-locked loop (DLL). The DAC shows 9.7 effective bits and 70 dB of spurious free dynamic range for a synthesized sine wave of 2 V/sub pp/ at 34 MHz and output rate of 200 MSPS. Altogether, the two DACs, their reference, and the DLL occupy an active area of 2.28 mm/sup 2/ and consume 693 mW at full speed.     

A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-/spl mu/m six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm/sup 2/.     

A stereo multibit ΣΔ DAC with asynchronous master-clockinterface

A two-channel multibit ΣΔ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1° phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-μm DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm×4 mm     

Nyquist电流型7位20MHz采样率CMOS数模转换器

介绍了一种高速7位DAC的设计及芯片测试结果,该DAC选取高5位单位电流源,低2位二进制电流源的分段结构。考虑了电流源匹配、毛刺降低以及版图中误差补偿等方面的问题来优化电路。流片采用0.35μmChartered双层多晶四层金属工艺,测试结果表明在20 MH z的采样频率下,微分非线性度和积分非线性度分别小于±0.2 LSB和±0.35 LSB。该DAC的满幅建立时间是20 ns,芯片面积为0.17 mm×0.23 mm。电源电压为3.3 V,功耗为3 mW。     

A 14-b, 100-MS/s CMOS DAC designed for spectral performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm ² of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed