HfO2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在p-Si(100)衬底上制备了HfO2栅介质层,研究了HfO2高k栅介质的电流传输机制和应力引起泄漏电流(SILC)效应.对HfO2栅介质泄漏电流输运机制的分析表明,在电子由衬底注入的情况下,泄漏电流主要由Schottky发射机制引起,而在电子由栅注入的情况下,泄漏电流由Schottky发射和Frenkel-Poole发射两种机制共同引起.通过对SILC的分析,在没有加应力前HfO2/Si界面层存在较少的界面陷阱,而加上负的栅压应力后在界面处会产生新的界面陷阱,随着新产生界面陷阱的增多,这时在衬底注入的情况下,电流传输机制就不仅仅是由Schottky发射机制引起,而存在Frenkel-Poole发射机制起作用.同时研究表明面积对SILC效应的影响很小.     

Al_2O_3栅介质的制备工艺及其泄漏电流输运机制

利用室温下反应磁控溅射结合炉退火的方法在P Si(10 0 )衬底上制备了Al2 O3 栅介质层,研究了不同的溅射气氛和退火条件对Al2 O3 栅介质层物理特性的影响.结果表明:在较高温度下N2 气氛中退火有助于减小泄漏电流;在O2 气氛中退火有助于减少Al2 O3 栅介质中的氧空位缺陷.对Al2 O3 栅介质泄漏电流输运机制的分析表明,在电子由衬底注入的情况下,泄漏电流主要由Schottky发射机制引起,而在电子由栅注入的情况下,泄漏电流可能由Schot tky发射和Frenkel Poole发射两种机制共同引起.     

Al2O3栅介质的制备工艺及其泄漏电流输运机制

利用室温下反应磁控溅射结合炉退火的方法在P-Si(100)衬底上制备了Al2O3栅介质层,研究了不同的溅射气氛和退火条件对Al2O3栅介质层物理特性的影响.结果表明:在较高温度下N2气氛中退火有助于减小泄漏电流;在O2气氛中退火有助于减少Al2O3栅介质中的氧空位缺陷.对Al2O3栅介质泄漏电流输运机制的分析表明,在电子由衬底注入的情况下,泄漏电流主要由Schottky发射机制引起,而在电子由栅注入的情况下,泄漏电流可能由Schottky发射和Frenkel-Poole发射两种机制共同引起.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究.研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化.应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加,击穿电荷减少,也会造成关态漏泄漏电流的退化.栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生.热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动,这解释了源区一侧栅氧化层损伤的产生原因.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

微波管栅发射问题的研究

利用离子束辅助沉积技术在 Mo栅极上镀上并注入一层 Hf膜,对镀后的样品进行了形貌、结构、成份、膜厚及 Mo、Hf界面分析。将样品进行电子管模拟栅发射试验,栅极温度为 650℃,试验 1000h以上基本无栅发射电流,可以提高栅控管的可靠性和寿命。实验结果表明,阴极中的活性物质Ba蒸发到镀Hf的 Mo栅极表面,Ba,Hf和O2能形成化合物,从而有效抑制栅极发射电流。     

MOS晶体管中辐照引起的陷阱正电荷的强压退火

电离辐射在 MOS结构的 Si O2 层中建立正陷阱电荷 ,这些正陷阱电荷在正强栅偏压( + 2 0 V)下迅速减少 ,这是由于正栅压引起硅衬底中的电子向 Si O2 层隧道注入 ,从而与陷阱正电荷复合 .正栅压退火不仅对 N沟 MOS结构非常有效 ,对 P沟 MOS结构也有一定的影响 .给出了辐照后的 NMOS和 PMOS晶体管在强正栅压下退火的实验结果 ,阐明了正栅压下的“隧道退火”机理 .     

含N超薄栅氧化层的击穿特性

研究了含 N超薄栅氧化层的击穿特性 .含 N薄栅氧化层是先进行 90 0℃干氧氧化 5 m in,再把 Si O2 栅介质放入 10 0 0℃的 N2 O中退火 2 0 min而获得的 ,栅氧化层厚度为 10 nm.实验结果表明 ,在栅介质中引入适量的 N可以明显地起到抑制栅介质击穿的作用 .分析研究表明 ,N具有补偿 Si O2 中 O3≡ Si·和 Si3≡ Si·等由工艺引入的氧化物陷阱和界面陷阱的作用 ,从而可以减少初始固定正电荷和 Si/ Si O2 界面态 ,因此提高了栅氧化层的抗击穿能力     

表面预处理对HfO2栅介质MOS器件漏电特性的影响

采用反应磁控溅射方法,在Si衬底上制备了不同表面预处理和不同后退火处理的HfO2栅介质MOS电容。测量了器件的C-V和I-V特性,并进行了高场应力实验。器件的界面特性和栅极漏电机理分析表明,界面态和氧化物陷阱是引起大的栅极漏电流的主要因素。采用新颖的O2 CHCl3(TCE)表面预处理工艺,可以显著降低界面态和氧化物陷阱密度,从而大大减小栅极漏电流和SILC效应。     

含氟超薄栅氧化层的抗击穿特性研究

对含 F超薄栅氧化层的击穿特性进行了实验研究。实验结果表明 ,在栅介质中引入适量的 F可以明显地提高栅介质的抗击穿能力。分析研究表明 ,栅氧化层的击穿主要是由于正电荷的积累造成的 ,F的引入可以对 Si/Si O2 界面和 Si O2 中的 O3 ≡ Si·与 Si3 ≡ Si·等由工艺引入的氧化物陷阱和界面陷阱进行补偿 ,从而减少了初始固定正电荷和 Si/Si O2 界面态 ,提高了栅氧化层的质量。研究结果表明 ,器件的击穿电压与氧化层面积有一定的依赖关系 ,随着栅氧化层面积的减小 ,器件的击穿电压增大。     

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO₂) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n⁺-polySi) gate. The analysis utilizes the measured gate current density J_G at high oxide fields E_ox in 5.4 to 12 nm thick SiO₂ films between 25 and 300℃. The leakage current measured up to 300℃ was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n⁺-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO₂ conduction band (CB). It was observed that PF emission current I_PF dominates FN electron tunneling current I_FN at oxide electric fields E_ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO₂ films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.     

Polarity asymmetry of stress and charge trapping behavior of thin Hf- and Zr-silicate layers

In this paper, reliability aspects of thin Zr- and Hf-silicate layers are addressed by analyzing the stress induced leakage current (SILC) and charge trapping during constant voltage stress (CVS) and constant current stress (CCS). Voltage polarity and temperature effects on the degradation of the layers are also studied. SILC in silicate layers is found to be strongly polarity dependent and it is suggested that the damage causing it is near silicate/Si interface. SILC has a transient component and its recovery is explained by the trapping/detrapping of traps participating in Poole–Frenkel conduction. Unlike SiO₂, hot carrier induced damage is not the main mechanism for SILC creation. Therefore, the origin of SILC in silicate layers is distinctly different to SiO₂.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Trap generation and breakdown processes in very thin gate oxides

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.     

Conduction mechanisms in MOS gate dielectric films

This paper reviews the conduction mechanisms in the gate dielectric films of MOSFETs for VLSI and ULSI technologies. They include Fowler–Nordheim tunneling, internal Schottky (or Pool–Frenkel) effect, two-step (or trap-assisted) tunneling, shallow-trap-assisted tunneling, and band-to-band tunneling. The current transport in the gate dielectric films is manly controlled by film material composition, film processing conditions, film thickness, trap energy level and trap density in the films. In general, for a given gate dielectric film, the current transport behaviors are normally governed by one or two conduction mechanisms.     

Stress-induced leakage current in p+ poly MOS capacitorswith poly-Si and poly-Si0.7Ge0.3 gatematerial

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si_0.7 Ge_0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.