An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices

Network security for mobile devices is in high demand because of the increasing virus count. Since mobile devices have limited CPU power, dedicated hardware is essential to provide sufficient virus detection performance. A TCAM-based virus-detection unit provides high throughput, but also challenges for low power and low cost. In this paper, an adaptively dividable dual-port BiTCAM (unifying binary and ternary CAMs) is proposed to achieve a high-throughput, low-power, and low-cost virus-detection processor for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dual-port dynamic AND gates. The dual-port designs reduce power consumption and increase storage efficiency due to shared storage spaces. In addition, the dividable BiTCAM provides high flexibility for regularly updating the virus-database. The BiTCAM achieves a 48% power reduction and a 40% transistor count reduction compared with the design using a conventional single-port TCAM. The implemented 0.13 mum processor performs up to 3 Gbps virus detection with an energy consumption of 0.44 fJ/pattern-byte/scan at peak throughput.     

A Planar UWB Diversity Antenna

A planar dual-port diversity antenna, operating with broadside and/or conical radiation patterns in H-planes, is presented for ultrawideband (UWB) applications. The proposed antenna consists of a suspended square patch with a thick stem underneath. A broadband differential feeding strip is used to feed the square patch. The measured gain for the broadside mode is 8.4–10.3 dBi from 3.1 GHz to 5.2 GHz (50.6%), and the conical mode 3.2–5.1 dBi from 3.1 GHz to 4.9 GHz (45%). The measured reflection coefficients $(vert S _{11} vert, vert S _{22} vert)$ are less than -10 dB over the frequency ranges and the isolation $vert S _{21} vert $ between the two ports is greater than 13.5 dB. The operation of the differential feeding strip on the antenna is discussed. Both pattern diversity and partial polarization diversity are achieved for this antenna.      

基于DDS芯片AD9858的复杂雷达信号模拟器设计

设计了一种基于直接数字合成（DDS）的复杂雷达信号模拟器。与传统的频率合成方法相比,DDS合成信号具有频率切换时间短、频率分辨率高、相位变化连续等诸多优点。利用双口随机存储器的高速数据存取与现场可编程门阵列器件的高性能、高集成度相结合,可以克服传统DDS设计中的很多不足,从而设计开发出性能优良DDS系统。     

A tunable optoelectronic oscillator based on a tunable microwave attenuator

A novel realization of a wideband tunable optoelectronic oscillator (OEO) based on dual-port electrode Mach–Zehnder modulator (DMZM), a tunable microwave attenuator (TMA), and a chirped fiber Bragg grating (CFBG) is proposed and demonstrated. By simply adjusting the power ratio between the two arms of DMZM, the chirp of the DMZM will be tuned, and the center frequency of the microwave photonic filter will be tuned. When the OEO loop in the proposed system is closed, the output frequency of OEO is determined by the microwave photonic filter, and a high spectral purity microwave signal with a tunable frequency from 5.8 to 11 GHz is generated. The single sideband (SSB) phase noise of the generated signal could reach −107.4 dBc/Hz at an offset frequency of 10 kHz.     

倒装焊对探测器频响特性影响的理论分析及工艺优化

针对光探测器在倒装焊过程中频响性能恶化的问题,建立等效电路模型分析出其原因,并通过优化倒装焊工艺条件予以有效解决。该电路模型包括探测器芯片、过渡热沉和倒装焊环节三个部分。基于倒装焊后探测器的S11参数和频响曲线提取出倒装焊环节特征参数,确认焊点接触电阻过大是引起探测器频响下降的主要原因。通过优化倒装焊工艺条件,有效减小了焊点接触电阻,基本消除了倒装焊对探测器频响特性的影响。     

基于双DSP的雷场侦察图像实时压缩及存储方法研究

以2个TMS320C62xx为核心处理器,实现大面积雷场图像的实时压缩和传输.使用双口RAM实现2个DSP之间的高速通信,利用EMIF、EXBUS及McBSP实现与外围设备的通信,通过FIFO进行数据的输入/输出缓冲,并以CPLD来控制系统的逻辑时序.     

Tunable Optical Mode Ferromagnetic Resonance in FeCoB/Ru/FeCoB Synthetic Antiferromagnetic Trilayers under Uniaxial Magnetic Anisotropy

Ferromagnetic resonance (FMR) is one of the most important characteristics of soft magnetic materials, which practically sets the maximum operation speed of these materials. There are two FMR modes in exchange coupled ferromagnet/nonmagnet/ferromagnet sandwich films. The acoustic mode has relatively lower frequency and is widely used in radio‐frequency/microwave devices, while the optical mode is largely neglected due to its tiny permeability even though it supports much higher frequency. Here, a realistic method is reported to enhance the permeability in the optical mode to an applicable level. FeCoB/Ru/FeCoB trilayers are carefully engineered with both uniaxial magnetic anisotropy and antiferromagnetic interlayer exchange coupling. This special magnetic structure exhibits a high optical mode frequency up to 11.28 GHz and a maximum permeability of 200 at resonance. An abnormally low inverse switch field (<200 Oe, less than 1/5 of the single layer) is observed which can effectively switch the system from optical mode with higher frequency into acoustic mode with lower frequency. The optical mode frequency and inverse switch field can be controlled by tailoring the interlayer coupling strengths and the uniaxial anisotropy fields, respectively. The tunable optical mode resonance thus can increase operation frequency while reduce operation field overhead in FMR based devices.     

六方氮化硼薄膜制备及其压电响应的研究

采用射频(RF)磁控溅射的方法,通过改变工艺参数在n型Si(100)片上制备六方氮化硼(h-BN)薄膜。通过傅立叶红外(FTIR)光谱仪,X射线衍射(XRD)仪进行结构表征,原子力显微镜(AFM)进行表面形貌和压电性能表征。测试结果表明,在射频功率为300 W、衬底温度为500℃、工作压强在0.8Pa、N2与Ar流量比为4∶20和衬底偏压在-200V时制备的六方BN薄膜具有高纯度、高c-轴择优取向,颗粒均匀致密,粗糙度为2.26nm,具有压电性并且压电响应均匀,符合高频声表面波器件基片高声速、优压电性要求。薄膜压电性测试研究表明,AFM的PFM测试方法适用于纳米结构半导体薄膜的压电性及其压电响应分布特性的表征。     

微声学器件封装特性研究

分别采用TO-CAN和SMT形式对微声学器件进行了封装,并对封装后的器件进行了耦合腔测试和指向性测试。测试结果表明,通过减小前入声孔直径大小,能够抑制微音频器件的高频响应;另外通过采用不同的封装结构参数,能够实现∞形和心脏形指向性的微超声器件。     

Design techniques for high-throughput BiCMOS self-timed SRAMs

Design techniques for a high-throughput BiCMOS self-timed SRAM are described. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192×9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-μm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency     

双口RAM在图像处理系统中的应用研究

基于图像处理系统实时性和大数据量冲突的问题,提出了在图像处理系统中使用双口RAM的方法。介绍了双口RAM的功能和特点,以IDT70V09芯片为例给出了图像处理系统中应用双口RAM的系统架构设计、硬件接口设计、系统软件设计以及FPGA和DSP对双口RAM操作软件的详细设计,并针对双口RAM的端口争用问题与解决方法进行了详细讨论,对系统的印制板设计和电路调试提出了建议。最后对图像处理系统进了功能测试,证明了采用双口RAM设计的系统的稳定性和可行性。     

Wideband simple cylindrical dielectric resonator antennas

Bandwidths of the coaxial fed and aperture coupled cylindrical dielectric resonator antennas (DRAs) with broadside radiation patterns are enhanced by exciting the HEM/sub 11/spl Delta// (1相似文献   

用于WLAN(802.11b)基带处理器芯片组的高速ADC及DAC的测试

简要介绍了清华大学微电子研究所设计的用于WLAN(802.11b)基带处理器芯片组的高速ADC及DAC,以及爱德万测试如何使用WVFG/WVFD实现高速ADC蛐DAC的测试。     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion     

High-performance, 0.1 μm InAlAs/InGaAs high electron mobilitytransistors on GaAs

This letter describes the material characterization and device test of InAlAs/InGaAs high electron mobility transistors (HEMTs) grown on GaAs substrates with indium compositions and performance comparable to InP-based devices. This technology demonstrates the potential for lowered production cost of very high performance devices. The transistors were fabricated from material with room temperature channel electron mobilities and carrier concentrations of μ=10000 cm² /Vs, n=3.2×10¹² cm^-2 (In=53%) and μ=11800 cm²/Vs, n=2.8×10¹² cm^-2 (In=60%). A series of In=53%, 0.1×100 μm² and 0.1×50 μm² devices demonstrated extrinsic transconductance values greater than 1 S/mm with the best device reaching 1.074 S/mm. High-frequency testing of 0.1×50 μm² discrete HEMT's up to 40 GHz and fitting of a small signal equivalent circuit yielded an intrinsic transconductance (g_m,i) of 1.67 S/mm, with unity current gain frequency (f_T) of 150 GHz and a maximum frequency of oscillation (f_max) of 330 GHz. Transistors with In=60% exhibited an extrinsic g_m of 1.7 S/mm, which is the highest reported value for a GaAs based device     

高端口隔离度双极化贴片天线设计

针对WLAN的MIMO系统应用要求,并缩小天线所占据的空间,设计具有高端口隔离度的双极化贴片天线。采用共面带状线馈电的环形贴片和微带馈电单极贴片相结合形式,利用环形辐射元与单极子辐射元产生正交线极化的特点,实现双馈双极化天线。实验结果显示,所设计天线的工作频带范围为2.27~2.73GHz,端口隔离度在31dB以上。同时,单极结构辐射元主极化要比其交叉极化大25dB以上,环形结构辐射元在较大空间范围内其主极化比交叉极化大23dB以上。这表明所设计双馈双极化天线具有较高的端口隔离度,且有良好的极化纯度。通过结构参数调整,还可望同时覆盖5.8GHz频段,以满足IEEE802.11n标准要求。     

Low power dual-port CMOS SRAM macro design

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 μm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers     

行波型球形超声电机定子的优化设计

提出了一种具有同步调心结构的球形超声电机,建立了电机驱动力矩的数学模型,重点对行波型定子进行结构优化设计。利用ANSYS对定子进行模态分析和谐响应分析;通过灵敏度分析确定结构参数优化变量,以最大干扰模态与工作模态频率差和最大定子表面振幅为优化目标,建立设计空间的响应面模型,采用多目标遗传算法(MOGA)进行优化求解得到Pareto前沿,最终确定结构参数并对定子试制件进行定扫频实验。测试结果表明,优化后的定子工作模态频率±2 kHz内无干扰模态产生,且定子两相驻波表面质点具有较大振幅,满足使用要求。     

An 8-ns random cycle embedded RAM macro with dual-port interleavedDRAM architecture (D2RAM)

A novel fast random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²RAM) has been developed. The macro exploits three key circuit techniques: dual-port interleaved DRAM architecture, two-stage pipelined circuit operation, and write before sensing. Random cycle time of 8 ns under worst-case conditions has been confirmed with a 0.25-μm embedded DRAM test chip. This is six times faster than conventional DRAM