板级模拟电路仿真收敛性技术研究

电路仿真不仅应用于电路设计阶段,也用于电路故障诊断中。电路仿真结果能够为建立电路测试诊断知识库提供重要的参考信息。本文简要介绍了电路仿真收敛性的相关理论,分析了板级模拟电路直流分析和瞬态分析的仿真收敛性问题,深入探讨了电路仿真技术的原理和发展,重点研究了新的电路仿真算法,并将其应用于模拟电路仿真系统中。     

业界要闻

我国深亚微米集成电路设计技术获重大突破 由上海交通大学大规模集成电路研究所研制成功的“深亚微米集成电路设计技术”,日前通过教育部专家鉴定。 上海交大在“深亚微米集成电路设计技术”研究中所包含的器件建模、延时网络、参数提取、数据库及管理、逻辑综合、电路模拟、版图没计、物理验证等设计技术总体水平达到国际先进水平。其中在0.25μm级深亚微米芯片设计技术中的“逻辑综合与物理设计一体化理论”,属国际首创。交大今后将与国内有关企业加强合作,尽快实现我国深亚微米集成电路设计技术及芯片的产业化。     

我们需要编写新的SPICE吗?

模拟电路仿真与模拟集成电路设计一直是不可分割的.集成电路设计师理解和设计电路的方式已经深深地受到了SPICE仿真器的影响.     

VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素，随着集成电路(IC)进入超深亚微米发展阶段，芯片工作速度不断增加，集成度和复杂度提高，而工艺容差减小的速度跟不上这种变化，因此参数成品率的研究越来越重要．本文系统地讨论了参数成品率的模型和设计技术研究进展，分析不同技术的特点和局限性．最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向．     

深亚微米集成电路中的ESD保护问题

本文对深亚微米工艺所引起的集成电路抗静电能力下降的原因和传统保护电路设计的缺陷进行了深入的阐述,从制造工艺、保护电路元件和保护电路结构三方面对深亚微米集成电路中的ESD 保护改进技术进行了详细论述     

IP核设计——中国集成电路产业发展的突破口

随着集成电路设计水平和工艺技术的提高，集成电路规模越来越大，芯片设计规模和设计复杂度也急剧提高，工艺流程呈现专业化，EDA设计逐步发展和完善。到了九十年代出现了SoC芯片（系统级芯片），即可以在一个芯片上包括了CPU、DSP、逻辑电路、模拟电路、射频电路、存储器和其它电路模块以及嵌入软件等，并相互连接构成完整的系统。由于系统设计日益复杂，设计业出现了专门从事开发各种实现不同功能的IP核的专业公司，     

EDA技术与FPGA设计应用

EDA技术是现代电子设计技术的核心，它在现代集成电路设计中占据重要地位。随着深亚微米与超深亚微米技术的迅速发展，FPGA设计越来越多地采用基于VHDL的设计方法及先进的EDA工具。本文详细阐述了EDA技术与FPGA设计应用。     

一种改进的片内ESD保护电路仿真设计方法

对现有的片内ESD保护电路仿真设计方法进行了改进,使之适用于深亚微米工艺.文中设计了新的激励电路以简化仿真电路模型;增加了栅氧化层击穿这一失效判据;使用能量平衡方程描述深亚微米MOSFET的非本地输运,并对碰撞离化模型进行了修正;使用蒙特卡罗仿真得到新的电子能量驰豫时间随电子能量变化的经验模型.最后使用文中改进的仿真设计方法对一个ESD保护电路进行了设计和验证,测试结果符合设计要求.     

毫米波CMOS集成电路的现状与趋势

随着深亚微米和纳米CMOS工艺的成熟,设计和实现低成本的毫米波CMOS集成电路已成为可能.简述了毫米波CMOS技术的发展现状,介绍了毫米波CMOS集成电路的关键技术,即晶体管建模和传输线建模,并给出了毫米波CMOS电路的最新进展和发展趋势.     

VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.     

An evaluation of deep-submicron CMOS design optimized for operation at 77 K

Using a careful and insightful analysis of the possible benefits of 77 K CMOS in submicron technology from a decade ago [1], the development of 77 K CMOS in present-day deep submicron technology is evaluated. It is found that the basic principles from the earlier study—that the real benefit of 77 K CMOS operation is the ability to provide “pure” scaling of the threshold voltage and thus to allow aggressive super-scaling of MOS transistor dimensions—not only holds in present-day CMOS processes, but is even more important in that regard. A detailed analysis of CMOS technology, digital circuit behavior, and analog circuit behavior is provided. It is noted that not only does properly-designed 77 K CMOS technology provide opportunities; it also addresses some of the most fundamental difficulties facing CMOS technology and CMOS circuit design.     

Enhanced analog “yields” cost-effective systems-on-chip

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to “design-in” quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits     

Study of swing potential on deep submicron on-chip interconnect

The low energy limit of signal on deep submicron on-chip interconnect is deduced from Shannon's communication theorem considering the influence of noise. Based on this energy limit, the analytic model of minimum swing potential considering transmission line effects is constructed. Applying the analytic model to interconnect in deep submicron technology nodes from 0.18 to 0.05 μm, it is shown that the swing potential with present low-swing technique such as SDVST could be reduced further by 70–95% according to the analysis of this work. Correspondingly, by using the low-swing interconnect technique with the minimum swing potential obtained in this work, the decrement of interconnect dynamic power dissipation can be further decreased by about 10–20% of their original one by using SDVST technique, and that of interconnect propagation delay, by one third. Furthermore, the maximum interconnect length is evaluated with a minimum swing potential value in interconnect design. All the results are valuable for interconnect performance optimization, such as repeater insertion in deep submicron circuits. As an application, the design of low swing potential interconnect with interface circuit is introduced.     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

Simulation and fabrication of submicron channel length DMOStransistors for analog applications

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1-μm-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7° implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator     

Body ballast resistor enhances ESD robustness of deep sub-micron CMOS circuit

In this paper, the body ballast resistor design is introduced in electrostatic discharges (ESD) protection circuit for deep submicron CMOS integration circuit applications. With having the resistor, the ESD strength, turn-on resistance and trigge-on speed are greatly modulated. Those good characteristics enhance the efficiency of ESD protection circuit and keep the gate-oxide away from ESD damages. The consequence is caused from the fact that body ballast resistor builds up a positive substrate potential during the ESD stressing; consequently, reduces source to substrate barrier height. It should be further addressed that only a few design complexity is added, which is especially useful in deep sub-micron ULSI manufacturing.     

Advanced BCD technology with vertical DMOS based on a semi-insulation structure

A new semi-insulation structure in which one isolated island is connected to the substrate was proposed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical device without extra internal interconnection structure was presented. The manufacturing of the new semi-insulation structure employed multi-epitaxy and selectively multi-doping. Isolated islands are insulated with the substrate by reverse-biased PN junctions. Adjacent isolated islands are insulated by isolation wall or deep dielectric trenches. The proposed semi-insulation structure and devices fixed in it were simulated through two-dimensional numerical computer simulators. Based on the new BCD technology, a smart power integrated circuit was designed and fabricated. The simulated and tested results of Vertical DMOS, MOSFETs, BJTs, resistors and diodes indicated that the proposed semi-insulation structure is reasonable and the advanced BCD technology is validated.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.