单电子晶体管全加器电路设计

基于单电子晶体管(SET)的I-V特性和二叉判别图数字电路的设计思想,改进了二叉判别图(BDD))单元,得到了一类基本逻辑门电路,进而提出了一种由11个BDD)单元即22个SET构成的全加器电路单元。SPICE宏模型仿真结果验证了设计的正确性。     

基于 PDSOI工艺的抗 SET锁相环设计

基于0．35μm PDSOI工艺设计了一款输出频率范围为700M Hz-1．0GHz的锁相环电路,利用Sentaurus TCAD工具对其进行单粒子瞬变（SET ）混合模拟仿真,确定其SET敏感部件并建立SET分析模型,分析了SET与锁相环系统参数之间的关系．通过增加由一个感应电阻、一对互补运算放大器和互补SET电流补偿晶体管组成的限流电路并利用多频带结构降低了VCO的增益,显著提升了锁相环的抗SET性能．仿真结果表明,CP中发生SET后VCO控制电压Vc的波动峰值、锁相环的恢复时间以及输出时钟的错误脉冲数明显降低,分别为未加固锁相环的43．9％、49．7％和29．1％,而辐射加固前后 VCO的基本结构变化不大,其SET轰击前后无明显变化．     

面向低功耗的全加器优化设计

在对现有全加器电路研究分析的基础上，提出了基于传输管逻辑的低功耗全加器。电路采用对称结构，平衡了电路延迟，消除了毛刺，降低了功耗。经PSPICE在0．24μm工艺下模拟仿真，与已发表的全加器电路的性能进行比较。测试结果表明，改进的新全加器功耗可减小77．5％，同时能耗也是最低的。     

一种基于多输入单电子晶体管的比较器电路

基于多输入单电子晶体管(SET)的Ⅰ-Ⅴ特性和CMOS数字电路的设计思想,提出了一种由18个互补型SET和1个双栅极SET构成的1位比较器电路结构.该比较器优点为:利用一个双栅极SET的固有特性,使异或逻辑块得到了简化,减少了晶体管的数目;电压兼容性好,输入和输出高低电平都接近0.02 V和0 V;静态总功耗低(6.42 pW).仿真结果验证了电路的正确性.     

基于多数决定逻辑非门的低功耗全加器设计

全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。     

量子全加器构造的探讨

本文探讨了由Toffoli门和受控非门等量子逻辑门构成低位输入、低位输出的量子全加器的电路，并分析了该种量子全加器的变换操作。通过比较推导出有多位输入、多位输出量子全加器的电路组合规律．     

高性能全加器设计技术研究

文章讨论几种全加器的设计,并设计了一种基于数据选择器的全加器。通过HSPICE仿真,与其他结构的全加器进行比较,结果表明基于数据选择器的全加器在功耗与速度上比其他结构的全加器有较大提高。     

量子元胞自动机全加器的性能分析与设计

作为一种新型的纳米器件,量子元胞自动机（Quantum-dot cellular automata,QCA）有望取代传统CMOS器件.本文总结了目前已提出的三种全加器（Full Adder,FA）架构,通过概率转移矩阵（Probabilistic Transfer Matrix,PTM）分析找出其中最稳定的架构,进一步地,利用这三种全加器分别构建串行加法器,并从复杂度、不可逆功耗、成本等方面进行比较,结果发现性能最优的全加器架构为MR Azghadi FA.随后,选择该架构提出了一种针对全加器的新型逻辑门和共面QCA全加器电路,并应用此全加器设计了多位串行加法器,经对比分析表明,本文所提出的全加器电路在面积、元胞数和功耗等方面均有较大改进,且具有很好的扩展性.     

DSP中低功耗全加器的改进设计

在充分研究现有典型全加器结构的基础上,提出了一种结合传输管逻辑和传输门逻辑特点的新型全加器。该全加器采用对称的XOR/XNOR结构,减少了电路延迟,降低了功耗。基于0.18μm CMOS工艺,采用HSPICE对电路进行仿真。结果表明,与典型结构全加器相比,提出的全加器在电路功耗和延迟功耗积(PDP)方面的改进分别为22%和27%。     

一种新型的电流模式曲率补偿带隙基准源

提出了一种新型的低压带隙基准源,与传统的带隙基准不同,该电路引入了第三个电流,以消除双极型晶体管射基电压的温度非线性项,从而实现曲率补偿。采用0．18μmCMOS工艺进行设计验证,HSpice仿真结果表明,室温下的输出电压为623mV,-55～＋125℃范围内的温度系数为4．2ppm／℃,1．0～2．1V之间的电源调整率为0．9mV／V。     

基于单电子晶体管的动态全加器电路设计

基于单电子晶体管的I-V特性,运用CMOS动态电路的设计思想,提出了一种基于单电子晶体管的全加器动态电路,利用SPICE对设计的电路进行了仿真验证,分析了电荷分享问题.相对于静态互补逻辑电路的设计方法,基于单电子晶体管的动态逻辑电路不仅克服了单电子晶体管固有的电压增益低的缺点,而且器件数目也大幅减少.多栅SET的使用可以减少电荷分享问题对动态电路的影响.     

基于单电子晶体管的数字滤波器硬件实现

基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。在讨论数字滤波器硬件实现原理基础上，由这三个单元电路实现了一个二阶IIR滤波器。SET的SPICE宏模型验证了设计的正确性。     

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.     

An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phaseclocked logic-flip-flops

An 8-b adder composed of carry-increment full adders has been designed and implemented in a standard 1.0 μm CMOS technology and successfully tested up to 800 MHz. The performance of this adder is based on a fine-grain pipeline technique using so called “logic-flip-flops”. These edge triggered logic-flip-flops are true single-phase clocked and reduce the cycle time of pipeline stages by combining logic and storage. For low power applications, the power consumption of the 8-b adder can be reduced from 777 mW (5 V Vdd, 800 MHz) down to 144 mW (3 V Vdd, 480 MHz)     

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.     

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder     

Optimized transmission gate-based CMOS full adders: design and analysis

By analysing the output characteristics of individual pass transistors in a transmission gate (TG) based CMOS full adder, it is possible to use fewer transistors to implement addition. Various simplified full adders with different numbers of transistors are tested using Pspice simulation. Comparison of these full adders is based on the maximum allowable offset voltages of each node in the full adder configuration. The simplest architecture with a driving output inverter only requires 14 transistors instead of the original 22, as proposed by Zhuang and Wu. Since the simplest architecture is conditional, minimizing the threshold voltage of pass transistors and a design that is more robust are desired in order to increase the fabrication yield. A 16-transistor full adder is optimized for the trade-off between area and reliability. By converting two transistors of an XOR gate into an inverter, this full adder is demonstrated to perform better than an 18-transistor full adder, especially while the inputs are degraded.     

Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8?V, 75°C demonstrate power reduction by 59.4% in case of 1?bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1?bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45?V applied in active mode improves the maximum operating frequency by 16% in case of 1?bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.     

Proposed low power, high speed adder-based 65-nm Square root circuit

This paper focuses on the design of a 1-bit full adder circuit using Shannon’s theorem and adder-based non-Restoring and Restoring Square Rooter circuits. The proposed adder and Square Rooter schematics were developed using DSCH2 CAD tool, and their layouts were generated with Microwind 3 VLSI CAD tool. The Square Rooter circuits were analysed using standard CMOS 65-nm features with a corresponding voltage of 0.7 V. BSIM 4 was used to analyse the parameters. The proposed adder-based Square Rooter simulated results of the proposed adder with those of CPL, Static Energy Recovery Full (SERF), and CMOS adder cell-based Square Rooter circuits; the proposed adder-based Square Rooter circuit gives better results than the other adder-based Square Rooter circuits. We then compared the results with published results and observed that the proposed adder cell-based Square Rooter circuit dissipates lower power, responds faster, and has a higher EPI and higher throughput.