一种适用于3D NAND闪存的分布式功率级LDO设计

由于3D NAND闪存芯片面积较大,其电源分布网络庞大、复杂,既需要满足多个块(block)并行读写时所需的600 mA峰值电流要求,也需要满足芯片在待机状态下的低功耗要求-针对以上问题,设计了一种为3D NAND闪存芯片进行供电的无片外电容的分布式功率级LDO电路.通过设计Active和Standby两种工作模式下的...     

突破HDD的瓶颈用SSD取代1.8英寸HDD

使用NAND闪存大幅度缩短计算机启动时间的方法主要有两种。一个是用集成了NAND闪存的SSD取代HDD，另一种是NAND闪存和HDD共用技术。     

基于NAND闪存的自适应闪存映射层设计

NAND闪存以非易失性、低功耗、抗辐射等优点,被广泛应用于嵌入式系统中.由于闪存写前需先擦写和高坏块率等硬件特性,成为其在应用中的障碍,需要通过闪存映射层进行存储管理.通过给出一种基于NAND型闪存的自适应闪存映射技术,对数据访问模式进行判断,为不同的访问模式提供不同粒度的地址映射方法,用于充分利用NAND闪存的优势克服其缺点,提高系统性能.该方法在Linux系统上予以实现,并进行了性能测试.     

开放式大容量NAND Flash数据存储系统设计与实现

完成了一种基于NAND Flash存储介质的开放武大容量数据存储系统设计,包括硬件系统以及软件系统的设计,并在软件设计中重点提出了应用于NAND闪存的数据管理算法,通过二级地址映射,按块中的脏页数回收脏块和按时间标记转移静态信息实现坏块管理,均匀损耗.该设计能为各种存储器件提供底层的NAND闪存存储系统,使其能方便快速地存储数据而不需要考虑NAND闪存的物理特性.     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

从NAND闪存中启动U-BOOT的设计

本文介绍了S3C2410中NAND闪存的工作原理,分析了从NAND闪存启动U-BOOT的设计思路,并着重描述了NAND闪存支持U-BOOT的程序设计,移植后U-BOOT在嵌入式系统中运行良好。     

基于QC-LDPC码的空间CCD图像NAND闪存存储纠错

为了提高空间CCD相机图像NAND闪存存储可靠性,提出一种基于QC-LDPC码的NAND闪存纠错算法。首先,分析了NAND闪存纠错信道模型;然后,根据闪存特点提出了一种基于QC-LPDC(1056,1024)码的NAND闪存纠错算法,为了加快编码效率提出了校验矩阵构造和高效编码方法,设计的校验阵均是0和1,只有移位和加法运算,非常适合硬件实现;最后,使用地面检测设备对闪存纠错算法进行了试验验证。结果表明,闪存纠错算法能快速稳定、可靠地工作,计算复杂度比较低,算法复杂度仅具为O(N);算法纠错能力高,误码比(BER)为10-6时,本文算法比RS码多0.47dB编码增益;使用65nm CMOS单元库,系统工作频率为250MHz时解码器数据吞吐率达到7.2Gbps;低误码平层,在误比特率为10-8时未出现误码平层。本文的NAND闪存纠错算法满足了空间相机图像存储系统的应用。     

YAFFS文件系统在嵌入式Linux上的实现

本文分析了基于NAND闪存的文件系统YAFFS的有关特性。通过在嵌入式Linux上实现YAFFS的实例,介绍了在嵌入式系统中使用NAND闪存的方法。     

与NAND Flash正面交锋Spansion舞剑意在数据闪存市场

以往NOR闪存与NAND闪存的应用市场可说是泾渭分明,前者多为小容量、代码应用,后者则主要用于大容量数据存储.然而Spansion所推出的ORNAND闪存却极有可能打破这样的界线,因为它同时具备了NOR闪存的高可靠性和快速读写能力以及NAND闪存高容量、低成本特色,大有与NAND在数据闪存市场一争高低的能力.     

Spansion e.MMC存储新品提供更安全可靠的数据保护

近日,嵌入式市场闪存解决方案创新厂商Spansion公司宣布推出面向消费、通信和工业设备市场的工业级e.MMC NAND闪存系列。新的e.MMC NAND闪存提供8GB和16GB存储密度,工作温度范围为-40℃到＋85℃,可满足上述市场对可靠、更高密度存储日益增长的需求。最新推出的Spansione.MMC闪存系列完善了Spansion领先业界的并行和串行NOR闪存以及面向嵌入式应用的SLC NAND闪存产品组合。     

一种基于EJTAG快速在线烧写Flash的设计

介绍了MIPS的KITAG片上调试体系结构、调试流程，分析了当前在线烧写Flash的各种方法。并提出了一种新型的利用片上调试系统快速在线烧写Flash的设计。实验结果表明，该方案比现有方法的效率提高了88％。该方法已经成功运用在基于MIPSCPU的聚芯SoC的FPGA和ASIC版本中。     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-Vpower supply

A 512-Mb flash memory, which is applicable to removable flash media of portable equipment such as audio players, has been developed. The chip is fabricated with a 0.18-μm CMOS process on a 126.6-mm² die, and uses a multilevel technique (2 bit/1 cell). The memory cell is AND-type, which is suitable for multilevel operation. This paper reports new techniques adopted in the 512-Mb flash memory. First, techniques for low voltage operation are described. The charge pump, control of pumps, and the reference voltage generator are improved to generate internal voltage stably for multilevel flash memory. Next, a method for reducing total memory cost in the removable flash media is described. A new operation mode named read-modify-write is introduced on the chip. This feature makes the memory system simple, because the controller does not have to track sector-erase information     

A quick intelligent page-programming architecture and a shieldedbitline sensing method for 3 V-only NAND flash memory

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms     

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-μm flash memory process and successfully operated at a low voltage of 1.5 V     

Performance and reliability improvement of flash device by a novel programming method

The operating methods of flash memory device are worth studying due to the reliability issue. A novel programming method based on a new current mechanism is developed in this work to improve the performance and reliability of flash memory. Experimental results show that this novel programming method with higher gate current injection efficiency not only increases the operating speed but also improves the reliability. This reliability improvement can be attributed to the reduction of oxide-trap-charge generation and threshold-voltage shift.     

基于429总线的TMS320F2812程序的远程加载技术

介绍了TI公司数字信号处理器TMS320F2812的引导方式、Flash编程方法、Flash启动流程。在此基础上提出了一种基于429总线的TMS320F2812程序的远程加载方案,并详细阐述了软硬件的实现过程。该方案摆脱了Flash编程时对JTAG接口、RS232接口的依赖,非常适用于军用领域,具有较大的实用价值。     

一种基于FAT文件系统的NAND Flash坏块处理方法

NAND Flash具有高存储密度和高存储速率的特点,在嵌入式系统领域得到了广泛应用.但其固有的擦除机制和存在有坏块这一致命弱点,成为其在应用中的主要障碍.本文提出了一种应用于FAT文件系统上的坏块处理方法,使用Flash上其他的空闲块或者空闲空间来代替坏块,并将坏块在FAT表中作出标记以后不作使用.这种方法彻底屏蔽了坏块对上层应用的影响,并对存储介质没有造成任何不良影响,从而很好地克服了上述障碍.工程项目中的应用证明了其较高的可靠性.     

一种通用的NAND Flash参数识别方法

介绍了如何从未知参数NAND Flash芯片中,获得相应参数的一种通用方法,从而打破了这个界限,使得没有获得NAND Flash的datasheet的情况下仍然可以使用.     

Deep gradual flash fusion for low-light enhancement

In this paper, we propose gradual flash fusion, a new imaging concept that enables acquisition of pseudo multi-exposure images in a passive manner. This means that our gradual flash capture does not require any user-side manipulation (taking multiple shots or varying camera settings). Continuous high-speed capture naturally contains different intensities of flash in a single shooting. The captured gradual flash images, containing different information of the same scene, are fused to generate higher-quality images, especially in a low light scenario. For gradual flash fusion, we use a Generative Adversarial Network (GAN) based approach, where the generator is a tailored convolutional Auto-Encoder for image fusion. For the training, we build a custom dataset comprising gradual flash images and corresponding ground truths. This enables supervised learning, unlike most conventional image fusion studies. Experimental results demonstrate that gradual flash fusion achieves artifact-free and noise-free results resembling ground truth, owing to supervised adversarial fusion.