共查询到20条相似文献,搜索用时 15 毫秒
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Vijay Kumar Sharma Manisha Pattanaik Balwinder Raj 《International Journal of Electronics》2013,100(2):200-215
Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node. 相似文献
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Mehdi Dolatshahi Omid Hashemipour Keivan Navi 《AEUE-International Journal of Electronics and Communications》2012,66(5):384-389
In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/ID characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit. 相似文献
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Qiang Zhou Author VitaeAuthor Vitae Yici Cai Author Vitae Xianlong Hong Author Vitae 《Integration, the VLSI Journal》2009,42(3):340-345
Multi-threshold CMOS (MTCMOS) technology is an effective sub-threshold leakage power reduction method in CMOS circuits, which satisfies high-performance and low-power design requirements. The optimization of virtual supply network plays an important role in MTCMOS low-power design. Existing low-power works are mainly on gate level, without any optimization on physical design level, which can lead to a large amount of virtual supply networks. Merging the objective of virtual networks minimization into physical design, this paper presents (1) a low-power-driven physical design flow; (2) a novel low-power placement to simultaneously place standard cells and sleep transistors; and (3) the sleep transistor relocation technique to further reduce the virtual supply networks. Experimental results are promising for both achieving up to 28.15% savings for virtual supply networks and well controlling the increase of signal nets. 相似文献
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《Microelectronics Journal》2007,38(6-7):706-715
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wide range of applications domains, and particularly in electronic design automation (EDA). SAT is increasingly being used as the underlying model for a number of applications in EDA. This paper describes how to formulate two problems in power estimation of CMOS combinational circuits as SAT problems or 0–1 integer linear programming (ILP). In these circuits, it was proven that maximizing dissipation is equivalent to maximizing gate output activity, appropriately weighted to account for differing load capacitances. The first problem in this work deals with identifying an input vector pair that maximizes the weighted circuit activity. In the second application we attempt to find an estimate for the maximum power-up current in circuits where power cut-off or gating techniques are used to reduce leakage current. Both problems were successfully formulated as SAT problems. SAT-Based and generic Integer Linear Programming (ILP) solvers are then used to find a solution. The experimental results obtained on a large number of benchmark circuits provide promising evidence that the proposed complete approach is both viable and useful and outperforms the random approach. 相似文献
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Design optimization for performance enhancement in analog and mixed-signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed-signal circuits, using a 45 nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and digital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an “effective tunneling capacitance”, which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45 nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime. 相似文献
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本文提出了一种具有高计算效率和低硬件开销的门控时钟低功耗优化算法. 该算法在RTL级搜索数据通路的不可观察性(Observability Don′t Care). 采用RTL级逻辑信号总线ODC模型和基于路径ODC的有向图遍历模型,减少了ODC计算负荷,提升了计算效率,使ODC适用于超大规模集成电路的低功耗优化. 引入数据通路ODC条件概率作为门控信号产生的重要依据,对ODC条件概率高的通路优先插入门控逻辑,可以极低硬件开销实现高效门控时钟网络. 实验结果显示,本算法与传统ODC算法相比计算负荷平均降低8倍,功耗平均下降12.35%,面积开销平均减少13.44%. 相似文献
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对目前基于过渡金属硫族化合物(TMD)材料(MoS2、WSe2等)的互补金属氧化物半导体(CMOS)反相器电路相关研究进行了综述。总结了TMD材料的物理性质、制备方法和基于TMD的场效应晶体管器件的研究进展。对基于TMD的集成电路技术研究进行了介绍与分析。分别在结构设计、集成工艺、性能优化及电路集成等方面对基于TMD材料的CMOS反相器电路进行了总结与分析。介绍了两种集成结构及对应的工艺流程,详细分析了CMOS反相器电路性能优化的方法。最后指出了目前的关键挑战及未来的发展趋势。 相似文献
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Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies. 相似文献
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本文简单介绍了门控时钟技术应用于RTL级功耗优化的原理.针对具体的RTL实例,利用门控时钟技术实现了RTL的功耗优化.实验结果表明:在采用门控时钟技术后,设计的功耗得到了显著降低,而代价则是增加很小的芯片面积. 相似文献
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《Spectrum, IEEE》1996,33(6):72-73
For huge, complex circuits, checking design rules at a level of abstraction above the gate level can identify architectural problems early on. Today's more mature equivalence checkers require little user input, but are not able to verify the quality or correctness of an original design. By adding RTL-DRC capability to formal verification tools, they can be used to find and correct RTL design problems early in the design cycle, with little or no extra effort necessary on the part of the designer 相似文献
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根据数模混合集成电路系统级和行为级快速验证的需求,设计了一种卫星导航系统射频接收机前端的频率合成器。传统行为级模型一般是基于理想环路进行参数提取,误差较大。为此,首先,分别利用MATLAB和Verilog-AMS对频率合成器建立理想行为级模型与非理想行为级模型,并根据行为级模型提取与优化的环路参数,采用SMIC 180 nm CMOS工艺设计仿真电路级频率合成器;其次,建立MATLAB噪声模型,对电路级各个模块的噪声进行拟合,评估频率合成器系统的整体噪声性能。所提出的频率合成器设计方法对电路级设计具有前瞻性的指导,并有助于电路级的设计优化。 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(11):1488-1498
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Gaj K. Herr Q.P. Adler V. Brock D.K. Friedman E.G. Feldman M.J. 《Applied Superconductivity, IEEE Transactions on》1999,9(3):4591-4606
Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits 相似文献
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Sudhakar S. Mande Author Vitae 《Microelectronics Reliability》2011,51(12):2357-2365
This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (Vth) assignment technique for the design of low power nanoscale CMOS circuits. The proposed technique is based on the Plackett-Burman Design of Experiment method (PB-DOE) in which sensitivity of each transistor to delay variation due to change in its Vth is obtained. The various paths in the circuit are categorized into process sensitive and process-insensitive paths. Transistors in the process sensitive paths are assigned a high Vth to reduce the leakage power without affecting performance. The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-Vth assignment technique. Moreover, it is shown that the proposed algorithm can be easily extended to assign dual gate length circuits to achieve a further 20% reduction in the leakage power. The robustness of the proposed technique against process variations is demonstrated with extensive Monte Carlo Simulations. The versatility of the proposed approach to reduce the leakage power for a general CMOS circuit is demonstrated using a Manchester carry chain adder. 相似文献
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Lin Yuan Gang Qu 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(2):173-182
Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively. 相似文献