倒装芯片键合技术发展现状与展望

我国集成电路发展十二五规划中提到,大力发展先进封装和测试技术,推进高密度堆叠型三维封装产品的进程,支持封装工艺技术升级和产能扩充。阐述了先进封装技术中的倒装芯片键合工艺现状及发展趋势,以及国际主流倒装设备发展及国内应用现状,重点介绍了北京中电科装备有限公司的倒装机产品。国产电子装备厂商应认清回流焊倒装芯片键合设备市场发展,缩短倒装设备产品开发周期和推向市场的时间,奠定国产电子先进封装设备产业化基础;同时抓紧研发细间距铜柱凸点倒装和热压焊接技术,迎接热压倒装芯片工艺及其设备的挑战。     

叠层芯片应用的封装挑战与解决方法

叠层管芯封装的不断发展导致该技术能有效地在同一基底内增大电子器件的功能和容量,作为单个芯片。蜂窝电话及其它消费类产品中叠层芯片封装的应用增长促使能够在给定封装尺寸中封装多层芯片。介绍了叠层芯片封装技术中最主要是满足总封装高度的要求。用于叠层芯片封装的技术实现方法包括基片减薄、薄裸芯片贴装、小形貌引线键合、与无支撑的边缘键合以及小偏倒成形等。集中介绍了叠层管芯互连要求。介绍了倒装芯片应用中的正向球形键合、反向球形键合和焊凸凸焊技术,讨论了优点和不足。说明球形键合机的发展能够满足叠层芯片封装的挑战,即超低环形状、长引线跨距和悬空键合等。     

倒装芯片的底部填充材料和涂布

倒装芯片是当今半导体封装领域的一大热点,它既是一种芯片互连技术,更是一种理想的芯片粘接技术。以往后级封装技术都是将芯片的有源区面朝上,背对基板粘贴后键合(如引线键合和载带自动键合TAB)。而倒装芯片则是将芯片有源区面对基板,通过芯片上呈阵列排列的焊料凸点来实现芯片与衬底的互连。显然,这种芯片互连的方式能够提供更高的I/O密度。     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

GaAs芯片上倒装Si芯片的金凸点高度与键合工艺参数优化

随着射频集成电路向小型化、高集成方向发展，基于金凸点热超声键合的芯片倒装封装因凸点尺寸小、高频性能优越成为主流技术之一。以GaAs芯片上倒装Si芯片的互连金凸点为研究对象，通过有限元仿真方法，分析了温度和剪切力作用下不同高度金凸点的等效应力，得到金凸点的最优高度值。通过正交试验，研究键合工艺参数(压力、保持时间、超声功率、温度)对金凸点高度和键合强度的影响规律。通过可靠性试验，验证了工艺优化后倒装焊结构的可靠性。结果表明：键合工艺参数对凸点高度的影响排序为压力>超声功率>温度>保持时间，对剪切力的影响排序为压力>超声功率>保持时间>温度。     

BGA封装技术

本文简述了BGA封装产品的特点、结构以及一些BGA产品的封装工艺流程,对BGA封装中芯片和基板两种互连方法——引线键合/倒装焊键合进行了比较以及对几种常规BGA封装的成本/性能的比较,并介绍了BGA产品的可靠性。另外,还对开发我国BGA封装技术提出了建议。     

一种用于MEMS器件的Au-In倒装焊技术

介绍了Au-In键合在MEMS芯片封装中的应用.根据现有的工艺设备和实验条件对制备铟凸点阵列进行工艺设计,对铟凸点制备技术进行了研究,最终在硅圆片上制备了6 μm高的铟凸点阵列.在150～300℃下成功的进行了Au-In倒装键合实验.在300℃,0.3 MPa压力下键合的剪切强度达到了5 MPa.     

用于倒装芯片的晶片凸点制作工艺研究

倒装芯片在电子封装互连中占有越来越多的份额,是一种必然的发展趋势,所以对倒装芯片技术的研究变得非常重要。倒装芯片凸点的形成是其工艺过程的关键。现有的凸点制作方法主要有蒸镀焊料凸点、电镀凸点、微球装配方法、焊料转送、在没有UBM的铅焊盘上做金球凸点、使用金做晶片上的凸点、使用镍一金做晶片的凸点等。每种方法都各有其优缺点,适用于不同的工艺要求。介绍了芯片倒装焊基本的焊球类型、制作方法及各自的特点,总结了凸点制作应注意的问题。     

微波多芯片组件中的微连接

实现微波多芯片组件(MCM)电气互连的微连接技术是MCM组介绍微连接的三种基本方式丝焊键合、凸点倒装和载带贴装,侧重介绍了各连接方式的优势和连接形式并进行了分析.     

倒装焊接在压力敏感芯片封装工艺中的研究

胶粘引丝无法实现硅压力敏感芯片的小型化封装,无引线封装可以解决该问题。倒装焊接具有高密度、无引线和可靠的优点,通过对传统倒装焊接工艺进行适当的更改,倒装焊接可应用于压力敏感芯片的小型化封装。采用静电封接工艺在普通硅压力敏感芯片上制作保护支撑硅基片,在硅压力敏感芯片的焊盘上制作金凸点,调整倒装焊接的工艺顺序和工艺参数,实现了绝压型硅压力敏感芯片的无引线封装,为压力传感器小型化开辟了一条新路。试验结果表明该封装方式可靠性高,寿命长,具有耐恶劣环境的特点。     

焊料凸点倒装焊技术

介绍了倒芯片面阵式凸点制作、多层陶瓷基板焊盘制作及倒装焊各关键技术 ,并成功地获得了芯片与基板的互连。     

Flip Chip Bonding of 68 $times$ 68 MWIR LED Arrays

The flip chip bonding process is optimized by varying the bonding pressure, temperature, and time. The 68times68 mid wave infrared (MWIR) LED array was hybridized onto Si-CMOS driver array with same number of pixels. Each pixel has two indium bumps, one for cathode and another for anode. Both LED array and CMOS drivers have 15-mum-square Indium bump contact pads. We used Karl Suss FC150 flip chip machine for bonding of CMOS driver array onto LED array. From the LED current-voltage characteristics, it is concluded that the optimized flip chip bonding process results in uniform contact and very low contact resistance. Both electrical and optical characteristics of LED array after flip chip bonding are presented.     

倒装焊技术及应用

随着集成电路封装密度的提高,传统引线键合技术已经无法满足要求,倒装焊技术的发展能够解决该问题,并且得到了广泛的应用。文章介绍了倒装焊中的4种关键工艺技术,即UBM制备技术、凸点制备方法、倒装和下填充技术。其中凸点制备技术直接决定着倒装焊技术的好坏,为满足不同产品的需求,出现了不同的凸点制备技术,使倒装焊技术具备了好的发展前景。文章对各工艺技术的应用特点进行了阐述,并对倒装焊技术的发展前景进行了展望。     

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件—智能像素面阵 ,对倒装焊的工艺过程作了简要的介绍。该面阵采用铟做凸点材料 ,制作了输入输出数达 6 4× 6 4的凸点电极阵列 ,并采用回流焊的方式 ,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接 ,形成输入输出引线间距只有 80 μm的面阵器件     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

倒装焊对探测器频响特性影响的理论分析及工艺优化

针对光探测器在倒装焊过程中频响性能恶化的问题,建立等效电路模型分析出其原因,并通过优化倒装焊工艺条件予以有效解决。该电路模型包括探测器芯片、过渡热沉和倒装焊环节三个部分。基于倒装焊后探测器的S11参数和频响曲线提取出倒装焊环节特征参数,确认焊点接触电阻过大是引起探测器频响下降的主要原因。通过优化倒装焊工艺条件,有效减小了焊点接触电阻,基本消除了倒装焊对探测器频响特性的影响。     

PtSi 256×256 IRCCD微型化封装技术研究

采用倒装焊接技术,实现了PtSi 256×256 IRCCD微型化封装。对金属凸点、引线衬底的制备以及倒装焊接技术进行了研究。     

浅析贴片设备

由于表面组装技术不断地朝着小型化的方向发展 ,特别是在细间距、小直径的凸点和使用的焊剂等诸多因素的推动下 ,促使设备供应商根据倒装芯片技术的需求而研制新一代的贴装机。介绍了设备的制造厂家根据倒装芯片的特点 ,采用柔性 (软件 )方法和视觉系统等方案对现有的设备进行改型 ,从而实现了贴装设备的自动化。实践证明研制开发倒装芯片技术的自动组装技术可使生产率、材料和工艺设备取得明显的进步     

Test structure assembly for bump bond yield measurement on high density flip chip technologies

Modern flip chip technologies for imaging applications have achieved a very high integration level together with the possibility of large area assemblies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly. Consequently, yield tests become difficult, and an accurate measurement of it is often discarded. This problem is aggravated in medical applications, where the critical information can be limited to a few pixels, and therefore, yield should be very close to 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between an usable and a non-usable assembly. Therefore, quantitative and precise measurement of bump bond yield is needed to characterize the quality of any high density flip chip technology for these applications. In this paper, we present a newly developed test structure for electrical measurement of the bump bond yield of high density flip chip technologies, allowing both optimization and statistical control of the process. This test structure facilitates the identification of possible process deviations with precise quantitative yield measurements. It also allows to pin point any localized systematic failure in the bump bonding process. The test structure has been used to evaluate the yield of different flip chip technologies and has contributed to their fine optimization where necessary.