夹层式叠层芯片引线键合技术及其可靠性

随着电子封装技术的快速发展,叠层封装成为一种广泛应用的三维封装技术,该技术能够满足电子产品高性能、轻重量、低功耗、小尺寸等日益增长的需求。针对陶瓷封装腔体中的夹层式叠层芯片结构,键合点与键合引线处于陶瓷外壳空腔中,未有塑封料填充固定,区别于塑封叠层芯片封装器件,优化其引线键合技术,并做了相应可靠性评估试验。键合引线偏移长度最大为0.119 mm,未出现键合引线间隙小于设计值、碰丝短路等情况,为高可靠叠层芯片封装研究提供了参考。     

FOW在叠层CSP封装中的应用

随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的主要发展方向,叠层CSP封装具有封装密度高、互连性能好等特性,是实现三维封装的重要技术。针对超薄芯片传统叠层CSP封装过程中容易产生圆片翘曲、金线键合过程中容易出现0BOP不良、以及线孤（wireloop）的CPK值达不到工艺要求等问题,文中简要介绍了芯片减薄方法对圆片翘曲的影响,利用有限元（FEA）的方法进行芯片减薄后对悬空功能芯片金线键合（Wirebond）的影响进行分析,Filmon Wire（FOW）的贴片（DieAttach）方法在解决悬空功能芯片金线键合中的应用,以及FOW贴片方式对叠层CSP封装流程的简化。采用FOW贴片技术可以达到30％的成本节约,具有很好的经济效益。     

三维封装中引线键合技术的实现与可靠性

结合半导体封装的发展,研究了低线弧、叠层键合、引线上芯片、外悬芯片、长距离键合和双面键合6种引线互连封装技术;分析了各种引线键合的技术特点和可靠性.传统的引线键合技术通过不断地改进,成为三维高密度封装中的通用互连技术,新技术的出现随之会产生一些新的可靠性问题;同时,对相应的失效分析技术也提出了更高的要求.多种互连引线键合技术的综合应用,满足了半导体封装的发展需求;可靠性是技术应用后的首要技术问题.     

微电子封装中芯片焊接技术及其设备的发展

概述了微电子封装中引线键合、载带自动键合、倒装芯片焊料焊凸键合、倒装芯片微型焊凸键合等芯片焊接技术及其设备的发展 ,同时报告了世界著名封装设备制造公司芯片焊接设备的现状及发展趋势。     

晶圆叠层3D封装中晶圆键合技术的应用

论述了晶圆叠层3D封装中的典型工艺——晶圆键合技术,并从晶圆键合原理、工艺过程、键合方法、设备要求等方面对其进行了深入探讨;以期晶圆叠层3D封装能够应用到更加广泛的领域。     

叠层芯片封装技术与工艺探讨

论述了在叠层芯片封装的市场需求和挑战。首先采用在LQFP一个标准封装尺寸内,贴装2个或更多的芯片,这就要求封装体内每一个部分的尺寸都需要减小,例如芯片厚度、银胶厚度,金丝弧度,塑封体厚度等,要求在叠层封装过程中开发相应的技术来解决上述问题。重点就芯片减薄,银胶控制,无损化装片,立体键合,可靠性等进行了详细的介绍。     

先进封装中引线键合前等离子处理

当今的封装工程师们正面临许多挑战,包括降低封装成本策略、成品率提高工艺过程以及错综复杂的无损伤处理、小尺寸器件如多芯片模块、叠层封装和混合电路封装等。为了确保更高的器件可靠性和最小的制造成本,一种经过充分处理的表面因其能够显著提高键合质量和可靠性而成功地在先进封装的引线键合中扮演了重要角色。气体等离子技术能够用于在引线键合前清洗焊盘以改进键合强度和成品率。这是进行表面处理的一种十分有效的方法,它能够显著地改进制造能力、可靠性以及先进封装的成品率。主要讨论了在引线键合前表面处理采用的等离子体的类型及其相关的一些考虑,并评论了实验结果和环氧树脂排放污染的实例细节及有关衬底材料和器件特性。     

迎接三维封装的挑战

人们对蜂窝电话、PDA（个人数字助理）、数字相机和其他同类产品，要求尽可能小而轻，相应要求内部元件更小、更轻，还要薄。正在发展中的一种新封装技术能满足这些要求，就是多层芯片堆积封装，可以在同样面积的封装中获得多芯片功能。这种技术称为三维（3D）封装。纵然小面积封装具有明显的优点，但另外还要满足轻和薄两种需要，这就是当今封装技术面临许多挑战的原因。如果多层叠装的三维封装总高度要求满足一定厚度，则每层芯片的厚度必须相对应。目前，超薄组装的难题是开发芯片处理、内部连接及减小温度应力的工艺技术。任意功能或组成，必须满足“最大厚度预算”。本文列举了各种组成部分的厚度预算，并针对讨论的问题和可以满足挑战的不同内部连接技术，作了一一介绍。包括现行的球型健合和劈刀键合两种技术的比较及两种技术引线成弧的对策，并分析了各种技术的优缺点和极限。适当地评价了劈刀键合为什么可能成为一种适合于三维封装的连接技术，由于其超低弧线能力和其他标准劈刀特征，类似精细间距、连续针脚式跳压等。通过测试结果和电子扫描显微镜（SEM）照片证明了这些优点。     

3D-TSV封装技术

3D-TSV封装技术是实现多功能、高性能、高可靠且更轻、更薄、更小的系统级封装最有效的技术途径之一。3D-TSV封装关键技术包括:通孔制作、通孔薄膜淀积、磁控溅射、通孔填充、铜化学机械研磨、超薄晶圆减薄、芯片/晶圆叠层键合等。阐述了每种关键技术的工艺原理、技术特点、应用范围及发展前景,关键设备、关键材料以及TSV在三维封装技术中的应用。     

用低温圆片键合实现传感器和微电子机械系统器件的集成和封装

集成化是传感器和微电子机械系统(MEMS)的发展方向,即将传感功能、逻辑电路和驱动功能集成在一块单芯片上。未来的系统芯片将能通过集成的传感器和逻辑电路收集并分析外界数据,将这些数据传输到中央处理器并产生必要的动作或反应。讨论了这种系统集成芯片对于封装和集成的要求,并提出一种能够满足这种要求的低温键合技术。同时这种低温键合技术还具有气密性封装、保留透明窗口等优点。     

多层芯片应用中的封装挑战和解决方案

The continuous growth of stacked die packages is resulting from the technology‘s ability to effectively increase the functionality and capacity of electronic devices within the same footprint as a single chip.The increased utilization of stacked die packages in cell phone and other consumer products drives technologies that enable multiple die stacks within a given package dimension.This paper reviews t6he technology requirements and challenges for stacked die packages.Foremost among these is meeting package height is 1.2mm for a single die package.For stacked die packages,two or more die need to fit in the same area.That means every dimension in the package has to decrease,including the die thickness.the mold cap thickness,the bond line thickness and the wire bond loop profile.The technology enablers for stacked die packages include wafer thinning,thin die attachment,low profile wire bonding,bonding to unsupported edges and low sweep molding.     

多个叠层芯片封装技术

叠层芯片封装在与单芯片具有的相同的轨迹范围之内,有效地增大了电子器件的功能性, 提高了电子器件的性能。这一技术已成为很多半导体公司所采用的最流行的封装技术。文章简要叙述了叠层芯片封装技术的趋势、圆片减薄技术、丝焊技术及模塑技术。     

An investigation into warpages,stresses and keep-out zone in 3D through-silicon-via DRAM packages

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.     

Low-cost preparation method for exposing IC surfaces in stacked die packages by micro-abrasive blasting

An alternative method for exposing IC structures in stacked die packages is described in this paper. Conventional preparation of stacked die packages is complex and time-consuming, requiring costly equipment and experienced operators. This paper presents a method that uses the brittleness of silicon for controlled removal of silicon dies by micro-abrasive blasting. Micro-abrasive blasting affects only the top silicon die; lower dies are protected by the elastic adhesive or the die-attach tape. Dissolving the adhesive layers by chemical wet etching allows step-by-step removal of the stacked die layers. This method is fast and does not require expensive equipment.     

多层芯片堆叠封装方案的优化方法

芯片堆叠封装是提高存储卡类产品存储容量的主流技术之一,采用不同的芯片堆叠方案,可能会产生不同的堆叠效果.针对三种芯片堆叠的初始设计方案进行了分析,指出了堆叠方案失败的原因和不足.结合两种典型芯片堆叠封装结构(金字塔型和悬梁式)的特点,提出了一种采用转接芯片完成焊盘转移的优化方法,并举例进行了芯片堆叠封装方案的说明.最后,对转接芯片的制作及尺寸设计原则进行了研究.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Overview of Board-Level Solder Joint Reliability Modeling for Single Die and Stacked Die CSPs

Modeling can efficiently investigate the reliability of new packages, saving time, manpower, and cost for conducting actual tests; A good model is useful for short time-to-market. In this paper, only journal and technical magazine papers are reviewed, many of which report modeling analyses of single die and/or stacked die chip-scale packages. They are summarized regarding the methods, design parameters, and/or results. Brief comparisons are provided on similarities and differences of the effects of the common design parameters on solder-joint reliability. The effects of variations in materials, package designs, the number of dies, test conditions, and board geometry can be investigated efficiently by thermal cycling modeling or drop test modeling.      

用芯片嵌入技术创新移动应用中的2D和3D封装结构

智能移动装置的高速发展正在驱动更先进芯片封装技术的开发,以满足多功能集成和小型化的要求。传统的解决方案,如多芯片模块,可能无法同时满足高密度和小型化需求。而先进的2.5D硅基板TSV解决方案成本太高,特别是,在对成本敏感的消费类市场中不能使用。在这两者之间,芯片嵌入式封装可能是一个理想的解决方案,它不但有较高互联密度,较小封装尺寸,也可以实现多芯片集成。本文着重讨论了主动芯片的嵌入技术:二维扇出封装和三维封装叠加。二维结构包括扇出晶圆级封装和多层板中芯片嵌入,前者基于晶圆形式,后者基于型板形式。不同流程的选择造成成本和成品率的差异,也造成芯片放置时间的先后。本文讨论了"Die-First"、"Die-Mid"和"Die-Last"流程的优劣势。主动(有源)芯片嵌入的三维叠加有着与二维芯片嵌入类似的优势,只是主动芯片嵌入封装体的上端可以另外叠加封装体,以实现真正的SiP结构。本文还讨论了芯片嵌入技术的发展、未来增长、可能的封装形式和将来的路线图。     

An approach of numerical multi-objective optimization in stacked packaging

The main aim for the development of small electronic packages is supported by an ongoing development of portable communication devices. Thin silicon dies are believed to improve the device performance as well as its reliability. Additionally, novel packaging techniques such as stacked packaging reduce packaging cost and size, and improve the functionality and reliability. In the case of the stacked packages, wafers are stacked to form a 3D multi-chip package. On the other hand, the electronic market requires novel and efficient numerical designing tools to deal properly with the optimization. The goal of the current work was to design a reliable numerical model of the stacked package and afterwards perform numerical multi-objective optimization in reference to a number of variables, which influence the stacked package reliability.