EEPROM单元的电荷保持特性

利用理论推导和实验方法对电可擦除可编程只读存储器EEPROM单元在给定电压下的电荷保持特性进行了分析和研究,得出了EEPROM单元电荷保持能力的理论公式,得到了单元保持状态下的电特性曲线,发现在双对数坐标下,阈值电压的退化率与时间成线性关系.在假定电荷流失机制为Fowler-Nordheim隧穿效应的情况下,推出了EEPROM单元在给定外加电压下的电荷保持时间,并通过实验得出了简化的EEPROM单元寿命公式.     

共振隧穿二极管中的电荷积累效应——共振隧穿器件讲座(4)

介绍了共振隧穿二极管(RTD)中电荷积累效应,利用顺序隧穿模型分析了RTD中有电荷积累时器件各部分电压的再分布;并结合电压降局限于双势垒区和遍及整个RTD的两种情况,建立了电荷和电流方程;最后利用电荷积累效应解释了负阻区本征双稳态特性。     

FLOTOXEEPROM擦写过程中隧道氧化层陷阱俘获电荷的研究

本文首先从理论上分析FLOTOX EEPROM隧道氧化层中陷阱俘获电荷对注入电场和存储管阈值电压的影响,然后给出了在不同擦写条件下FLOTOX EEPROM存储管的阈值电压与擦写周期关系的实验结果,接着分析了在反复擦写过程中陷阱俘获电荷的产生现象.对于低的擦写电压,擦除阈值减少,在隧道氧化层中产生了负的陷阱俘获电荷;对于高的擦写电压,擦除阈值增加,产生了正陷阱俘获电荷.这一结果与SiO₂中电荷的俘获——解俘获动态模型相吻合.     

陷阱俘获存储器中电荷积累过程对保持特性的影响

本文通过数值模拟的方法对陷阱俘获存储器单元在多次擦写过程中的电荷积累过程进行了分析。由于多次擦写后陷阱电荷的积累,电荷之间的复合过程成为一个重要的问题。分析结果显示擦写过程中积累的空穴会对存储器的保持特性产生影响,同时在分析器件保持特性的时候电荷之间的复合机制必须加以考虑。     

浮栅隧道氧化层EEPROM中浮栅上电荷泄漏研究

本文从研究不同单元尺寸浮栅隧道氧化层EEPROM在不同状态、不同温度保存下阈值电压的变化入手,论述了浮栅隧道氧化层EEPROM中浮栅上电荷的泄漏机理,并提出了改进EEPROM保持特性的措施.     

陷阱电荷对GMLM工作电压的影响

光栅平动式光调制器(GMLM)依靠可动光栅在静电力作用下向下反射镜移动,从而改变光程差,实现光调制.结构中siO2绝缘层在外加电场作用下产生陷阱电荷,对器件的驱动特性产生影响.作者依据高斯定理,建立GMLM存在陷阱电荷情况下的电力学模型,分析了外加电场作用下,GMLM极板电荷的分布,以及外加电压与可动光栅位移的关系;比较了两种情况下(考虑与不考虑绝缘层陷阱电荷影响)工作电压变化情况.设计了实验方案,进行了实验研究.结果表明:由于陷阱电荷产生陷阱电压,使得产生相同位移需要的工作电压增加;充电时间越长,陷阱电荷产生的陷阱电压越大;实验结果与理论分析吻合.     

陷阱电荷对GMLM工作电压的影响

光栅平动式光调制器(GMLM)依靠可动光栅在静电力作用下向下反射镜移动,从而改变光程差,实现光调制.结构中siO2绝缘层在外加电场作用下产生陷阱电荷,对器件的驱动特性产生影响.作者依据高斯定理,建立GMLM存在陷阱电荷情况下的电力学模型,分析了外加电场作用下,GMLM极板电荷的分布,以及外加电压与可动光栅位移的关系;比较了两种情况下(考虑与不考虑绝缘层陷阱电荷影响)工作电压变化情况.设计了实验方案,进行了实验研究.结果表明:由于陷阱电荷产生陷阱电压,使得产生相同位移需要的工作电压增加;充电时间越长,陷阱电荷产生的陷阱电压越大;实验结果与理论分析吻合.     

SONOS存储单元数据保持特性退化研究

探讨了基于Fowler-Nordheim(F-N)隧穿进行编程、擦除的硅-氧化物-氮化物-氧化物-硅(SONOS)存储单元在擦写循环后的数据保持特性。分别通过分析和实验研究了擦写过程中操作电压大小对于VTH(编程)态、VTL(擦除)态存储单元数据保持性能退化的影响。对于VTH态单元,其数据保持性能退化程度受操作电压大小的影响不明显,电荷流失速度主要受温度影响；而VTL态单元数据保持性能退化程度受操作电压大小的影响较大,电荷流失速度与温度的关系不明显。通过对比不同操作条件下进行擦写循环后的数据保持性能退化程度,总结了有利于减小SONOS存储器数据保持性能退化的操作条件。     

量子效应和小型化对隧穿晶体管特性的影响

基于二维器件仿真工具,研究了量子效应和小型化对双栅隧穿场效应晶体管的特性和可靠性的影响.隧穿晶体管中的量子效应除了带间隧穿,还包括量子统计效应和垂直沟道方向的量子限制效应.研究表明,量子统计效应和量子限制效应对隧穿晶体管的电流电压特性,特别是正偏压温度不稳定性(PBTI)是非常重要的.另外,随着沟道长度和体硅厚度的缩小,隧穿晶体管的电流电压特性和可靠性都得到了改善,但在保持相同等效氧化层厚度的情况下,使用高介电常数的栅介质不会改善器件的电流电压特性及可靠性.     

电子倍增CCD中电荷载流子倍增寄存器的分布式等效电路模型

为了研究电子倍增电荷耦合器件(EMCCD)中电荷载流子倍增寄存器(CCM)内部电荷的倍增及转移特性,提出了一种适用于CCM的电荷传输机制仿真的分布式等效电路模型.利用泊松方程求解了均匀掺杂条件下CCM单元的电势分布,通过基尔霍夫电压定律(KVL)得到了该单元的最大电势表达式,从而得到了其分布式等效电路.同时,结合该单元...     

EEPROM as an analog storage device, with particular applications inneutral networks

The use of EEPROM as a compact, high-precision, nonvolatile, and reconfigurable analog storage element is investigated, with particular consideration given to the modifiable weight storage and analog multiplication problems in the hardware implementation of a neural network. Industry-standard digital EEPROM cells can be programmed to any analog value of threshold voltage, but programming characteristics of different devices on the same chip vary. The programming window of a single device also narrows with cycling. These phenomena necessitate the use of a feedback-based programming scheme. Stressing at high temperature suggests that charge retention is good even at 175°C. The linear variation of threshold voltage with temperature implies that temperature compensation of EEPROM is no more complicated than its conventional MOSFET counterpart. The drain current in the saturation region is found to be a quadratic function of drain voltage when the floating-gate-to-drain overlap capacitance is adequately large. A differential circuit that uses this property to generate the multiplication function required of neural net synapses is proposed     

Modeling of the intrinsic retention characteristics of FLOTOXEEPROM cells under elevated temperature conditions

A model for the intrinsic retention characteristics of FLOTOX EEPROM cells is presented, which is based on the temperature dependence of the Fowler-Nordheim emission current. This model which has been successfully tested on single-poly-FLOTOX EEPROM cells, enables the device lifetime to be calculated for given memory operating conditions, instead of being extrapolated as is usually done. The sensitivity of the retention characteristics to several technological parameters is also investigated. It is expected that this intrinsic retention model (with minor modifications) will also be applicable to FLASH EEPROM cells     

A nonvolatile semiconductor memory device in 6H-SiC for harsh environment applications

An electrically erasable programmable read-only memory (EEPROM) cell fabricated on a 6H-SiC substrate is reported. It is the first fully functional SiC EEPROM device. This device uses a generic double-polysilicon-gate configuration. It has been tested at both room temperature and elevated temperatures, up to 200/spl deg/C, to demonstrate full programmability. The threshold voltage shifts between programmed and erased states, at all tested temperatures, are larger than 4.5 V. In both states, the device functions satisfactorily as an n-type MOSFET. Charge retention time is more than 24 h at room temperature.     

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.     

A single poly EEPROM cell structure for use in standard CMOSprocesses

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits     

高兼容CMOS工艺嵌入EEPROM技术

电可擦除只读存储器是非易失性存储器。文章介绍了高兼容常规CMOS工艺的一种嵌入式电可擦除只读存储器设计与工艺技术,对电可擦除只读存储器单元、高压MOS器件的结构与技术进行了研究。研究结果表明,我们设计的0．8μm电可擦除只读存储器单元Vpp电压在13V～15V之间能够正常工作,擦写时间小于500μs,读出电流大于160μA／μm;在普通CMOS工艺基础上增加了BN＋埋层、隧道窗口工艺,成功应用于含嵌入电可擦除只读存储器的可编程电路的设计与制造。     

A multilevel approach toward quadrupling the density of flashmemory

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.