基于GPU的等值面提取与绘制*

利用图形硬件的并行性将六面体网格数据映射为纹理,从每个六面体中提取等值面片,并将其绘制到纹理而得到最终等值面。基于Cg着色器编程语言实现三维电磁环境表现的实验结果表明,该方法有效地减轻了CPU负担,提高了等值面提取速度,适合实时应用。     

用鞍点保证拓扑正确的快速等值面提取技术

等值面提取是研究三维数据场可视化的有效方法。针对已有的一些等值面提取算法存在的二义性问题,提出了用鞍点保证拓扑正确的快速等值面提取算法。用二线性插值和三线性插值函数来近似计算立方体表面和内部点的值,根据立方体中面鞍点和体鞍点个数的不同,将立方体剖分成不同数目的四面体。这种剖分只和原始数据的属性有关,与给定的等值无关,因此在数据不变的情况下只需要剖分一次。最后,用分层分组的方法将四面体分类到不同组中,避免在等值面提取过程中访问那些不含有等值面的四面体,从而提高了算法的速度。该算法在等值平滑变化或是随机变化时都能保持良好的特性。     

移动立方体算法与移动四面体算法的对比与评估

等值面提取在标量场体数据可视化和隐函数曲面显示中具有重要应用,经典算法包括移动立方体算法和移动四面体算法,其核心是在立方体或四面体体素单元中用线性的三角面片逼近原始曲面.文中以可计算的代数曲面为例,对上述2种等值面提取算法的逼近精度、时间和空间效率等方面进行了详细的对比,为各种应用中等值面提取算法的选取提供了参考依据.     

基于医学体数据生成四面体网格的方法

为了从医学体数据直接构造四面体网格,提出一种基于栅格的网格生成算法.该算法的主要思想是从背景栅格中提取并填充代表区域边界的等值面.首先,对医学体数据进行预处理与采样,构建一个背景栅格.其次,用对偶方法从栅格提取三角表面网格,用于分段线性逼近等值面.然后,对栅格中所有位于等值面之内或与等值面相交的立方体,用预定义的模板分解成四面体单元.最后,用Laplacian平滑技术优化四面体网格.在均匀网格的基础上,研究了自适应网格生成算法,在保持网格几何精度的同时精简单元数量,以提高有限元计算效率.给出了从CT数据生成人体股骨远端四面体网格的实例,该网格模型被用于虚拟膝关节镜手术.     

面向四面体网格生成的Delaunay refinement器官表面重建

为满足生物医学仿真系统对器官几何模型在Delaunay表面重构和四面体建模两方面的需求,提出一种面向四面体网格生成的Delaunay refinement表面重构算法.算法将从医学体数据中经过等值面提取和简化的初始表面作为输入和边界限定条件,为每个限定点计算局部特征尺寸并构建保护球,计算保护球与限定线段的交点并与限定点一起作为初始点集,生成Delaunay辅助四面体网格,引入一个迭代细分过程恢复边界,最终获得Delaunay重构表面.针对细分过程中的收敛性问题,文中给出了详细的理论证明和算法实例.此外,通过Delaunay四面体生成的对比实验表明该算法在Delaunay器官表面重构和四面体建模两方面兼具有效性和优越性.     

一种新的抽取等值面的四面体分解方法

Marching Cubes算法是一种从三维数据场中抽取等值面的简单有效的算法。然而，该算法并不能保证抽取出的等值面的拓扑同三维数据场的数据保持一致，即等值面的拓扑存在二义性。解决这个问题的方法是，将三维数数据场中每一个立方体网格单元分解为五个四面体单元，从每一个四面体单元中抽取等值面。但是，在分解过程中由于分解二义义性的存在，等值面的拓扑仍然存在二义性。本文采用24-分解方法解决了这个问题，生成了拓扑正确的等值面。     

基于多尺度等值面设计传递函数

在体绘制中传递函数将体数据转换成光学参数,因此体绘制的效果直接由传递函数决定.本文提出了基于多尺度等值面设计传递函数的高效方法.该方法通过梯度阈值提取边界体元来简化数据场,然后将提取等值面的目标函数的计算化简为累加的拉普拉斯加权的直方图极值的计算.最后对直方图进行多尺度平滑,利用提取出的多尺度等值面来设计高斯型传递函数,提高了等值面的准确度和传递函数的设计效率.     

一种改进的MC算法

为了对等值面与子等值面进行提取和分组,在MC算法原理的基础上,提出了一种改进的等值面提取与子等值面分组算法。该算法首先将数据场分解为点、棱边、面与体元的拓扑结构;然后在整个数据场范围内求所有棱边与等值面的交点,并在面内连接交点形成面与等值面的交线,交线在体元内连接生成空间多边形;接着通过三角化各个体元内的空间多边形得到由顶点表与三角形表组成的等值面数据;最后根据三角形在顶点处的连接关系,采用种子算法对属于同一子等值面的三角形与顶点进行标记,属于同一子等值面的顶点与三角形将被存放在独立的顶点表与三角形表中。实验结果表明,该算法可以高效地实现等值面提取与子等值面的分组。     

三维标量场并行等值面提取与绘制技术

通过研究并行等值面提取与绘制的各项关键技术要点,面向三维标量场的特点,在sort-last并行绘制模式的基础上提出一个三维标量场并行等值面提取与绘制框架.该框架在任务分配时采用静态分配的模式,在等值面提取时采用Marching Tetrahedra等值面提取算法,在并行绘制与场景合成时采用预先构建绘制节点控制模型的混合场景并行绘制合成算法.实验结果表明,该框架能够有效地提高大规模时变三维标量场的等值面提取与绘制效率,满足实际应用的需要.     

基于深度纹理的实时碰撞检测算法

结合层次包围盒和基于图形硬件的方法,以带深度纹理的包围盒替代物体的几何模型,利用图形硬件在纹理映射时进行深度比较,以实现碰撞检测.实验结果表明,与CULLIDE算法相比,文中算法执行效率更高且执行时间固定,具有较高的实时性.     

Hardware/software trade-offs for bitmap graphics on the blit

The Blit is an experimental bitmap graphics terminal built for research into interactive computer graphics on the UNIX time-sharing system. The hardware is inexpensive and the graphics functions are implemented entirely in software. Nevertheless, the graphics performance of the Blit is comparable or superior to some displays with special-purpose graphics hardware. This paper explains the paradox by referring to some principles of design: the hardware and software should be designed together to complement each other; carefully designed software can outperform infelicitous hardware; and simplicity of design leads to efficiency of execution. These principles are illustrated by examples from the Blit hardware and software and comparisons with other systems.     

A Survey of General-Purpose Computation on Graphics Hardware

The rapid increase in the performance of graphics hardware, coupled with recent improvements in its programmability, have made graphics hardware a compelling platform for computationally demanding tasks in a wide variety of application domains. In this report, we describe, summarize, and analyze the latest research in mapping general‐purpose computation to graphics hardware. We begin with the technical motivations that underlie general‐purpose computation on graphics processors (GPGPU) and describe the hardware and software developments that have led to the recent interest in this field. We then aim the main body of this report at two separate audiences. First, we describe the techniques used in mapping general‐purpose computation to graphics hardware. We believe these techniques will be generally useful for researchers who plan to develop the next generation of GPGPU algorithms and techniques. Second, we survey and categorize the latest developments in general‐purpose application development on graphics hardware.     

Window clipping methods in graphics accelerators

How some recently introduced graphics accelerators address window clipping is discussed. Some graphics accelerators can download the window-clip rectangle data structures used to represent the visible areas of a window to specialized RAM or hardware registers. These accelerators have special hardware and/or software to hold the clipping information and to properly clip graphics primitives. Others use window clip planes, which allow easy hardware representation of windows with arbitrary shape and complexity. They are ideal for clipping graphics output to nonrectangular windows because graphics output performance does not degrade as the number of rectangles needed to represent the window increases. CPU-based window clipping is examined. Devices in each of these classes are described     

Hardware-based view-independent cell projection

We present two implementations of a view-independent cell projection algorithm for off-the-shelf programmable graphics hardware. Both implementations perform all computations for the projection and scan conversion of a set of tetrahedra on the graphics hardware and are therefore compatible with many of the hardware-accelerated optimizations for polygonal graphics, e.g., OpenGL vertex arrays and display lists. Apart from our actual implementations, we discuss potential improvements on future, more flexible graphics hardware and applications to interactive volume visualization of unstructured meshes.     

Graphics hardware

Graphics hardware is far faster, smaller, cheaper, and more capable than 20 years ago, and it will obviously continue on that path. Memory and processor advances have let us move texture mapping and surface occlusion from software to hardware. We'll no doubt move more sophisticated modeling, lighting and imaging operations into future hardware. Chip I/O rates will continue to advance more slowly than transistor count and, as a result, graphics processors and memory will become ever more highly integrated. Putting memory and processor on the same chip will encourage massive parallelism, because on-chip bandwidth is staggering compared to that between chips. Integrating CPU and graphics is more a business issue than a technical one; game consoles represent one area where tight integration is mandatory. A more interesting question for looking 20 years into the future might be: what will be new? What fundamentally new capabilities can we predict as a result of hardware advances? What fundamentally new capabilities would we like to have but can't predict how, or if, we can achieve them? Advances in image generation hardware haven't fundamentally changed what an individual can actually do in an application; in contrast, some graphics hardware advances have created fundamental changes. We already have a start on some promising graphics hardware technologies that may enable fundamental changes in what we do in graphics over the next 20 years     

基于GPU图像直接体绘制算法分析与评价

近年来计算机图形硬件性能不断提高,利用硬件来实现体绘制过程中的某些环节以获取交互的绘制速率成为可能,是目前体绘制的研究热点。描述了基于GPU的光线投射法、2D纹理映射法和3D纹理映射法等典型算法,给出了各类算法的分析与性能评价,最后实现相关算法并得出实验结果。     

基于SOPC及图形加速引擎的座舱显示系统

提出一种基于可编程片上系统和图形加速引擎的飞机座舱综合显示系统设计方案。为避免图形加速引擎直接对帧存储器进行零碎操作导致的存储器操作瓶颈,引入图形缓存机制。根据图形像素的存储特点提出“远区域优先”图形缓存页面淘汰算法。对汉字及自定义位图等操作采取软硬件结合的方式达到系统性能和资源利用的平衡,利用硬件锁保证帧存储器一致性。通过对模块进行波形仿真实现系统级仿真结果的可视化验证。     

一个适合图形算法硬化的通用硬件设计

提高图形处理速度是计算机图形学硬件的发展方向。图形处理过程的硬化研究是至关重要的一环。本文介绍一个采用高速位片系列芯片和微程序控制技术的硬件系统，这一系统是一个方便的图形算法硬化的硬件仿真器。     

GRAAL: A Framework for Low-Power 3D Graphics Accelerators

The GRAphics AcceLerator (GRAAL) design-exploration framework is an open system that offers a coherent development methodology for hardware/software cosimulation and codesign of embedded 3D graphics accelerators. GRAAL incorporates tools to help visually debug graphics algorithms implemented in hardware and to estimate performance in terms of throughput, power consumption, and area.