基于FPGA动态部分重构的D/TMR系统设计

在空间环境中,系统的可靠性是保障系统正常运行的关键。针对此问题,提出了一种基于FPGA动态部分重构的D/TMR系统设计,正常工作时采用DMR系统,具有较低的面积开销和功耗;当系统出现故障时,利用FPGA部分动态重构技术切换为TMR系统,不需要额外的故障检测与定位电路,就可以保持系统功能的连续性与可靠性。经实验验证,该设计方案具有可行性。     

基于SRAM型FPGA的实时容错自修复系统设计方法

为提高辐射环境中电子系统的可靠性,提出了一种基于SRAM型FPGA的实时容错自修复系统结构和设计方法。该设计方法采用粗粒度三模冗余结构和细粒度三模冗余结构对系统功能模块进行容错设计;将一种细粒度的故障检测单元嵌入到各冗余模块中对各冗余模块进行故障检测;结合动态部分重构技术可在不影响系统正常工作的前提下实现故障模块的在线修复。该设计结构于Xilinx Virtex誖-6 FPGA中进行了设计实现,实验结果表明系统故障修复时间和可靠性得到显著提高。     

基于输出反馈特征结构配置的重构控制系统设计

推出了一种利用特征结构配置设计重构控制系统的新方法. 当故障后的系统满足m+r-1≥n的条件时, 通过重新设计一输出反馈增益阵, 使重构后的闭环故障系统的特征值全部恢复到故障前的位置, 特征向量也在可配置子空间中尽量接近故障前相应的闭环系统特征向量, 从而使重构后的系统性能最大程度地恢复到故障前的系统性能. 这种方法的优点是重构系统的稳定性可得到保证, 且计算输出反馈增益阵的算法相对简单. 应用实例和仿真结果说明本文方法的有效性.     

多分辨力传感器信息融合中的 故障检测与恢复

首先建立了一个具有故障检测与隔离功能的分散式滤波器结构，讨论了传感器及局部滤波器的故障检测与隔离算法，然后研究了系统重构与故障恢复方法。在此基础上，通过引入小波变换提出了一种多分辨力传感器信息的动态融合方法。     

局部动态可重构FPGA进程式调度系统设计与实现

针对6G时代多样的边缘计算要求，基于FPGA上的可重构技术可以实现更低的时延同时提供多样性的服务。基于局部动态重配置的思路，使用ICAP接口对FPGA资源进行重新配置，从而实现FPGA逻辑上的局部动态可重构方案。借鉴操作系统中软件进程管理的思想，基于Linux操作系统中引入硬件进程的概念，这样可以将一整块FPGA资源划分为多个小的FPGA资源块，每一个小的可重构的FPGA资源块都可以抽象成为一个硬件进程，硬件进程实际并不运行在CPU上而是运行在FPGA逻辑资源区域中，在操作系统上只是硬件进程的软件语言描述。由此，设计出CPU加FPGA的硬件方案来实现局部可重构系统，并在Xilinx公司Zynq系列芯片上进行了验证，将FPGA硬件资源进行进程式调度以及资源分配，大大提高了FPGA硬件资源的利用率以及灵活性。     

自定义FPGA测试系统的设计与应用

根据CCD成像软件测试需要,提出了以virtex5系列FPGA器件为核心的软件测试系统,描述了系统软硬件结构,分析了软件测试功能和测试用例;对时序、功能、故障模式、可靠性等进行测试并讨论;采用FPGA测试充分发挥了并行运算处理的优势,并能够实现快速在线实时重构,实现实时测量;通过系统仿真和实际测量,验证了软件的各项性能指标满足设计要求,表明FPGA测试系统在实际的CCD成像软件系统测试中能够很好的模拟时序和故障状态,完成测试任务,可广泛用于航天、探测等领域.     

连续媒体服务器存储系统中的容错算法

连续媒体服务器(如VOD服务器)要对大量连续媒体数据(如声频、视频)进行管理,按一定速率为用户提供连续的媒体服务。因此,在这样的系统中,作为存储设备的磁盘阵列要具有高可靠性和一定的容错能力。文章提出一种基于奇偶检验的数据重构恢复算法,以保证系统中只有一个盘出现故障时,能使服务器及时重构出故障盘上的数据,并且算法充分利用了媒体流内在特性———回放时数据的连续性,与目前使用的标准故障恢复算法相比,大大减少了磁盘在线故障后数据重构过程的系统开销。最后通过分析、比较证明了算法的有效性。     

基于LMS算法的自适应逆可重构控制系统

针对多输入多输出(MIMO)飞控系统的可重构设计问题,提出了解耦控制与自适应逆控制(adaptive inverse control)相结合的控制策略.首先采用降阶线性动态逆(RLDI)设计了某型飞机的滚转角控制回路,以使飞机侧向运动的滚转与侧滑之间实现解耦;然后,考虑到当舵机出现故障以后系统性能的恢复问题,应用基于ε-滤波的LMS(least mean square)算法,在系统解耦的基础上构建了自适应逆控制系统,从而实现系统在舵机故障下的重构.仿真结果表明,这种基于改进的ε-滤波的LMS算法的自适应逆可重构飞行控制系统具有良好的系统故障恢复功能,表明了其在飞控系统中实施重构控制的有效性.     

实现FPGA回读功能的可重构系统设计

Xilinx Virtex系列FPGA具有配置逻辑可重构、配置数据可回读的特点，该文设计了基于Virtex FPGA的一种可重构系统。FPGA采用SelectMAP配置方式，在CPU和CPLD控制下实现了配置数据加载和回读的功能。给出了系统配置FPGA和回读其配置数据的流程及相应的波形图。 关键词：     

FPGA动态可重构理论及其研究进展

近年来,随着微电子技术和计算机技术的发展,尤其是大规模现场可编程门阵列FPGA的出现,实时电路重构技术逐渐成为国际学术界的研究热点;基于FPGA的重构系统具有自适应、自主修复特性,在空间应用中具有非常重要的作用;文章介绍了基于FP-GA动态可重构技术的原理、分类,重点讨论了动态可重构的实现方法及两种技术,并给出了系统重构设计的流程,同时,介绍了基于FPGA动态可重构技术已取得的成功应用,最后展望了FPGA动态可重构技术的发展前景,并指出了有待解决的问题.     

FlexRay总线技术在航天领域的应用

针对航天领域的CAN 总线技术,本文提出一种新的FlexRay 总线通信方式,并介绍了一种基于FPGA+ FlexRay 架构的处理模式,同时描述了FlexRay 总线的特点和工作原理,从协议上分析了FlexRay 总线在航天领域应用的可行 性,从芯片选用、原理设计、接口实现以及软件设计等方面阐述了FlexRay 总线在我国航天领域的应用。     

通用嵌入式32位RISC CPU设计概述

近年来,嵌入式微处理器在SoC设计中得到了广泛应用。嵌入式微处理器设计成为一个颇受欢迎的话题,其设计过程主要包括规格定义、指令集、体系架构、总线接口、顶层模块划分、子模块设计和验证、系统整合与调试、系统级验证、FPGA原型验证和软件开发环境等几方面。     

基于FPGA的五级流水线CPU

基于FPGA平台设计并实现了一种五级流水线CPU.它参考MIPS机将指令的执行过程进行抽象,把指令分成取值、译码、执行、访存、写回五级流水处理.首先设计系统级的结构,决定CPU的结构和指令系统.其次对整体结构进行分解,确定模块与模块之间的信号连接,采用VHDL实现CPU.最后通过Debug-controller调试软件对五级流水线CPU进行调试.结果表明了所设计的流水线CPU的有效性.     

Verification-Purpose Operating System for Microprocessor System-Level Functions

Microprocessor system-level functions that provide hardware support for software are difficult to verify on FPGA prototypes. Traditional FPGA verification involves running a general-purpose operating system such as Linux. However, such a GPOS is difficult to control, and debug is inefficient. The Verification-Purpose Operating System, on the other hand, simplifies debug and is easy to control. VPOS also significantly increases coverage over that of GPOS approaches.     

ArchSim: A System-Level Parallel Simulation Platform for the Architecture Design of High Performance Computer

High performance computer (HPC) is a complex huge system, of which the architecture design meets increasing difficulties and risks. Traditional methods, such as theoretical analysis, component-level simulation and sequential simulation, are not applicable to system-level simulations of HPC systems. Even the parallel simulation using large-scale parallel machines also have many difficulties in scalability, reliability, generality, as well as efficiency. According to the current needs of HPC architecture design, this paper proposes a system-level parallel simulation platform: ArchSim. We first introduce the architecture of ArchSim simulation platform which is composed of a global server (GS), local server agents (LSA) and entities. Secondly, we emphasize some key techniques of ArchSim, including the synchronization protocol, the communication mechanism and the distributed checkpointing/restart mechanism. We then make a synthesized test of some main performance indices of ArchSim with the phold benchmark and analyze the extra overhead generated by ArchSim. Finally, based on ArchSim, we construct a parallel event-driven interconnection network simulator and a system-level simulator for a small scale HPC system with 256 processors. The results of the performance test and HPC system simulations demonstrate that ArchSim can achieve high speedup ratio and high scalability on parallel host machine and support system-level simulations for the architecture design of HPC systems.     

Managing approximation models in collaborative optimization

Collaborative optimization (CO), one of the multidisciplinary design optimization techniques, has been credited with guaranteeing disciplinary autonomy while maintaining interdisciplinary compatibility due to its bi-level optimization structure. However, a few difficulties caused by certain features of its architecture have been also reported. The architecture, with discipline-level optimizations nested in a system-level optimization, leads to considerably increased computational time. In addition, numerical difficulties such as the problem of slow convergence or unexpected nonlinearity of the compatibility constraint in the system-level optimization are known weaknesses of CO.This paper proposes the use of an approximation model in place of the disciplinary optimization in the system-level optimization in order to relieve the aforementioned difficulties. The disciplinary optimization result, the optimal discrepancy function value, is modeled as a function of the interdisciplinary target variables, and design variables of the system level. However, since this approach is hindered by the peculiar form of the compatibility constraint, it is hard to exploit well-developed conventional approximation methods. In this paper, neural network classification is employed as a classifier to determine whether a design point is feasible or not. Kriging is also combined with the classification to make up for the weakness that the classification cannot estimate the degree of infeasibility.In addition, for the purpose of enhancing the accuracy of the predicted optimum, this paper also employs two approximation management frameworks for single-objective and multi-objective optimization problem in the system-level optimization. The approximation is continuously updated using the information obtained from the optimization process. This can cut down the required number of disciplinary optimizations considerably and lead to a design (or Pareto set) near to the true optimum (or true Pareto set) of the system-level optimization.     

基于MPLS的快速重路由故障恢复综合模型

传统的多协议标签交换(MPLS)快速重路由故障恢复算法存在报文延迟、失序、故障修复时间过长等问题。为此,提出一种基于MPLS的快速重路由故障恢复综合模型,对LDP消息进行扩展、使用全局恢复机制和局部恢复机制相结合的综合策略,采用新型临时路径计算方法。仿真结果证明,该故障恢复综合模型可以降低丢包率,缩短故障恢复时间。     

Quality-driven model-based architecture synthesis for real-time embedded SoCs

The recent spectacular progress in modern microelectronics created a big stimulus towards development of embedded systems. Unfortunately, it also introduced unusual complexity which results in many serious issues that cannot be resolved without new more adequate development methods and electronic design automation tools for the system-level design. This paper discusses the problem of an efficient model-based multi-objective optimal architecture synthesis for complex hard real-time embedded systems, when using as an example a system-level architecture exploration and synthesis method that we developed.     

基于FPGA的H.264帧内预测实现和优化

在使用硬件电路进行H.264编码时,为提高帧内预测运算速度,减少硬件电路面积,提出一种基于现场可编程门阵列(FPGA)的H.264帧内预测硬件电路的实现和优化解决方案。利用FPGA的并行处理能力和同模式下帧内预测数据冗余对硬件电路进行优化。使用Verilog语言进行模块设计,仿真平台为Modelsim,在Altera CycloneII EP2C20F484C上的实现,验证了该硬件电路结构的高效性及实用性。