论数字图书馆系统中WEB服务器性能优化的方法

由于在数字图书馆系统中流通着的大多是数字化的索引、文摘、全文、图像或音频视频等多媒体信息,对Web服务器性能有着较高的要求.结合实际工程的经验,从硬件实现手段(缓存服务器、均衡负载设备、Web双机镜像等)和软件实现手段(多层软件结构设计、应用部署等)等两个大方面论述如何提高Web服务器性能,以便使用户能够更快捷、高效、安全地使用数字图书馆应用系统.     

Intel64体系结构的数据预取机制及效果

数据预取是为缓解微处理器与DRAM之间速度差异而出现的隐藏访存延迟的方法。当前Intel各系列处理器都采用多种预取机制来加速数据和代码向Cache的移动,从而提升程序的性能。通过对Intel64体系结构存储层次的分析,剖析了X86/X64体系的数据预取机制,包括硬件预取和软件预取,并且分析了编译器对软件预取机制的支持。最后测试了Intel64体系结构数据预取对科学计算程序中紧嵌套循环性能的影响,总结出了影响数据预取有效性的几个因素。此项工作对在Intel平台上进行循环数组预取优化有指导意义。     

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

Radiation-induced soft error has become an emerging reliability threat to high performance microprocessor design. As the size of on chip cache memory steadily increased for the past decades, resilient techniques against soft errors in cache are becoming increasingly important for processor reliability. However, conventional soft error resilient techniques have significantly increased the access latency and energy consumption in cache memory, thereby resulting in undesirable performance and energy efficiency degradation. The emerging 3D integration technology provides an attractive advantage, as the 3D microarchitecture exhibits heterogeneous soft error resilient characteristics due to the shielding effect of die stacking. Moreover, the 3D shielding effect can offer several inner dies that are inherently invulnerable to soft error, as they are implicitly protected by the outer dies. To exploit the invulnerability benefit, we propose a soft error resilient 3D cache architecture, in which data blocks on the soft error invulnerable dies have no protection against soft error, therefore, access to the data block on the soft error invulnerable die incurs a considerably reduced access latency and energy. Furthermore, we propose to maximize the access on the soft error invulnerable dies by dynamically moving data blocks among different dies, thereby achieving further performance and energy efficiency improvement. Simulation results show that the proposed 3D cache architecture can reduce the power consumption by up to 65% for the L1 instruction cache, 60% for the L1 data cache and 20% for the L2 cache, respectively. In general, the overall IPC performance can be improved by 5% on average.     

Optimally designing caches to reduce P2P traffic

Traffic caused by P2P services dominates a large part of traffic on the Internet and imposes significant loads on the Internet, so reducing P2P traffic within networks is an important issue for ISPs. In particular, a huge amount of traffic is transferred within backbone networks; therefore reducing P2P traffic is important for transit ISPs to improve the efficiency of network resource usage and reduce network capital cost. To reduce P2P traffic, it is effective for ISPs to implement cache devices at some router ports and reduce the hop length of P2P flows by delivering the required content from caches. However, the design problem of cache locations and capacities has not been well investigated, although the effect of caches strongly depends on the cache locations and capacities. We propose an optimum design method of cache capacity and location for minimizing the total amount of P2P traffic based on dynamic programming, assuming that transit ISPs provide caches at transit links to access ISP networks. We apply the proposed design method to 31 actual ISP backbone networks and investigate the main factors determining cache efficiency. We also analyze the property of network structure in which deploying caches are effective in reducing P2P traffic for transit ISPs. We show that transit ISPs can reduce the P2P traffic within their networks by about 50-85% by optimally designing caches at the transit links to the lower networks.     

AES访问驱动Cache计时攻击

首先给出了访问驱动Cache计时攻击的模型,提出了该模型下直接分析、排除分析两种通用的AES加密泄漏Cache信息分析方法;然后建立了AES加密Cache信息泄露模型,并在此基础上对排除分析攻击所需样本量进行了定量分析,给出了攻击中可能遇到问题的解决方案;最后结合OpenSSL v.0.9.8a,v.0.9.8j中两种...     

低丢包率无线传感器网络S-MAC协议的研究

针对S-MAC协议的层间丢包问题,利用缓存队列原理提出了一种简化通信数据分组格式的S-MAC协议优化改进方案。结合TinyOS的主动消息机制在Mica2节点上实现了改进的S-MAC协议,并对MAC层的丢包率进行了测试。实验测试结果表明,优化改进后S-MAC协议较标准S-MAC协议在MAC层的丢包率上有明显的降低,提高了网络性能。     

片上多核Cache资源管理机制研究

随着片上多核成为处理器发展的主流和片上Cache资源的持续增长,Cache资源的管理已成为片上多核的关键问题。介绍了片上多核Cache资源管理的研究进展,依据研究内容将Cache资源的管理分为Cache划分和Cache共享两类。对Cache划分,探讨了其主要组成部分和一般形式,分析和比较了典型的片上多核Cache划分机制。对Cache共享,给出了其主要研究内容,并介绍和比较了几种主流的片上多核Cache共享机制。通过分析,认为软硬件协同管理的页划分应是未来片上多核Cache划分机制的研究重点;而片上多核Cache共享机制的研究则应从目标应用的Cache行为特征着手。     

一种高效SMP Cache一致性协议及其实现技术的研究

结点控制器是并行多处理机计算机系统设计中除CPU外的最复杂部件,随着设计工艺水平的提高,它的功能也日益增多。文章将深入介绍SMP多处理机系统结点控制器设计中的一种高效Cache一致性协议以及实现方面的关键技术。     

面向对象数据库管理系统的对象管理系统的研究

数据库是实现CAD/CAM系统集成的主要方法和工具。当前,面向对象数据库管理系统已成为数据库管理系统研究的主要方向,而对象管理是实现面向对象数据库管理系统的关键技术。本文结合华中理工大学CAD中心开发的面向对象数据库管理系统GHEODB的对象管理系统GHOMS,研究了对象管理系统的结构组成并给出了相关算法和加速机制     

WWW代理技术现状与改进方案

介绍了既是WWW服务器,又是WWW客户方的代理技术———Cache技术。并提出了WWW本地代理的公共Cache和辅助代理相结合的方案,既可往Cache和辅助代理中写入数据,又可从辅助代理中读数据。最后又描述了辅助代理管理模块的设计。