Vitamin D Compounds PRI-2191 and PRI-2205 Enhance Anastrozole Activity in Human Breast Cancer Models

1,25-Dihydroxycholecalciferol, the hormonally active vitamin D₃ metabolite, is known to exhibit therapeutic effects against breast cancer, mainly by lowering the expression of estrogen receptors and aromatase activity. Previously, the safety of the vitamin D active metabolite (24R)-1,24-dihydroxycholecalciferol (PRI-2191) and 1,25(OH)₂D₃ analog PRI-2205 was tested, and the in vitro activity of these analogs against different cancer cell lines was studied. We determined the effect of the two vitamin D compounds on anastrozole (An) activity against breast cancer based on antiproliferative activity, ELISA, flow cytometry, enzyme inhibition potency, PCR, and xenograft study. Both the vitamin D active metabolite and synthetic analog regulated the growth of not only estrogen receptor-positive cells (T47D and MCF-7, in vitro and in vivo), but also hormone-independent cancer cells such as SKBR-3 (HER-2-positive) and MDA-MB-231 (triple-negative), despite their relatively low VDR expression. Combined with An, PRI-2191 and PRI-2205 significantly inhibited the tumor growth of MCF-7 cells. Potentiation of the antitumor activity in combined treatment of MCF-7 tumor-bearing mice is related to the reduced activity of aromatase by both An (enzyme inhibition) and vitamin D compounds (switched off/decreased aromatase gene expression, decreased expression of other genes related to estrogen signaling) and by regulation of the expression of the estrogen receptor ERα and VDR.     

PSO优化多核RVM的模拟电路故障预测

针对模拟电路健康管理的特点，提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征，计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值，将多个核函数线性组合，并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明，该方法在小样本情况下，预测效果优于单一核函数的RVM模型，适用于健康管理中实时预测，具有较好的实用性。     

用于嵌入系统的超声电机驱动设计

为了在嵌入式控制系统中充分利用超声电机特有功能,对超声电机的驱动原理进行了研究,在分析了超声电机的驱动控制原理的基础上,提出了一种基于单片机控制超声电机的软硬件控制实现方法。利用单片机输出数字量作为控制信号,通过串行输入并行输出芯片扩展后,输出到超声电机驱动器,实现超声电机启动/停止/正反转的功能;通过扩展单片机数模转换,将单片机控制超声电机速度的数字信号转换为电压信号,实现超声电机的速度控制功能;利用运行脉冲宽度控制实现超声电机的位置控制功能,并将光电编码器实现超声电机的反馈,最后通过试验验证了单片机系统实现超声电机驱动设计。     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

A new realization scheme for dynamic PFSCL style

In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the issue by proposing a scheme which modifies the structure of a D-PFSCL gate. The modified gate exhibits AND/OR functionality and is used to realize various functions. Simulations have been carried out by implementing various functions and comparing their performance with the existing schemes at 1 GHz. The results of performance comparison with existing schemes indicates significant reuduction in gate count resulting in overall performance improvement.     

Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors

A 4^th-order Butterworth class-AB current-mode low-pass filter is proposed, based on second-generation Current Conveyors (CCII). Class-AB operation allows high-power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class-AB output buffer with error amplifiers: this topology is known to be sensitive to mismatch errors, which cause offsets in the error amplifiers, affecting the biasing current of the stage. This problem is solved via a control loop, which compensates the effect of mismatches. The technique is shown to be effective in Monte Carlo simulations with process variations and mismatches. Simulations have been carried out in 40 nm CMOS technology. The proposed filter achieves good power efficiency, thanks to the class-AB architecture, and good dynamic range, thanks to the closed-loop output buffer. A cut-off frequency of 6 MHz, with 184 μW of total quiescent power consumption, is achieved, with a THD of -55 dB and a SNR of 49 dB.     

A Global Maximum Error Controller Based Nonlinearity Aware TPWL Method for Reducing Nonlinear Systems

Abstract

Model order reduction is a common practice to reduce large order systems so that their simulation and control become easy. Nonlinearity aware trajectory piecewise linear is a variation of trajectory piecewise linearization technique of order reduction that is used to reduce nonlinear systems. With this scheme, the reduced approximation of the system is generated by weighted sum of the linearized and reduced sub-models obtained at certain linearization points on the system trajectory. This scheme uses dynamically inspired weight assignment that makes the approximation nonlinearity aware. Just as weight assignment, the process of linearization points selection is also important for generating faithful approximations. This article uses a global maximum error controller based linearization points selection scheme according to which a state is chosen as a linearization point if the error between a current reduced model and the full order nonlinear system reaches a maximum value. A combination that not only selects linearization points based on an error controller but also assigns dynamic inspired weights is shown in this article. The proposed scheme generates approximations with higher accuracies. This is demonstrated by applying the proposed method to some benchmark nonlinear circuits including RC ladder network and inverter chain circuit and comparing the results with the conventional schemes.     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

继电保护中多路模拟量采集系统的设计

介绍了一种基于高性能浮点DSP芯片TMS320C32、CPLD芯片XC95288和A/D采样芯片AD976组成的多路采集系统的工作原理以及设计方法。通过对第一路施加特殊的电压量,在CCS开发环境下读取采样缓冲区的值,并利用Matlab对采样数据进行了全波傅氏变换。此外,该系统已在继电保护中得到广泛应用,实践表明,该系统能较好地解决多路模拟量的采集,并确保了采样数据的安全可靠性。