一种Ka波段低相噪GaAs HBT压控振荡器

本文研究了一种采用GaAs HBT工艺实现的工作在Ka波段的压控振荡器。该振荡器采用共射级组态和对称式电容电感谐振腔结构以降低其相位噪声,采用π型反馈网络补偿180°相移。在片测试结果表明：偏离中心频率1 MHz处相位噪声为-96.47dBc/Hz,调谐范围为28.312到28.695GHz,在-6V电源电压下该振荡器直流功耗为18mA,振荡器芯片面积为0.7mm×0.7mm。     

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (C_in) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm², i.e. 0.315 mm².     

Reliability analysis of MOS varactor in CMOS LC VCO

The paper investigates the reliability of MOS varactor tuned voltage-controlled oscillators (VCO). Due to the stress induced threshold voltage shift of the MOS varactor, the resonant tank degrades and the center frequency and phase noise of VCO deviate. The behavior is modeled and an adaptive body biasing scheme is proposed to make VCO resilient to reliability. In the mean time it does not degrade the VCO performance. An LC VCO at 24 GHz carrier frequency with adaptive body biasing is compared with VCO without such biasing design in PTM 65 nm technology. The ADS simulation results show that the biasing design helps improve the robustness of the VCO in resonant frequency. The design reduces the frequency sensitivity of VCO by 20% when subjected to threshold voltage degradation.     

基于多相子载波生成和高增益射频振荡器的高数据率超宽带调频发射机

描述了高数据率超宽带调频(FM-UWB)发射机的系统结构和电路设计.该发射机采用内含8相环形振荡器的有限模小数分频型锁相环(PLL)生成频率键控正弦波信号,以降低子载波频率和噪声.该环形振荡器输出的差分正弦波信号直接调制高增益射频(RF)环形振荡器,生成带宽为2 GHz且满足UWB频谱掩膜的信号.在65 nm TSMC...     

基于V600ME14-LF的锁相环设计

介绍了一种基于S波段的VCO器件V600ME14-LF的锁相环的设计方案,并且已经在实践中实现了其主要功能;同时介绍了V600ME14_LF的主要性能和应用注意事项,V600ME14-LF器件可广泛应用在测试仪器和卫星通信等场合。     

A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...     

一种用于FPGA的270MHz到1.5GHz可重构多功能锁相环时钟发生器

本文设计实现了一种用于FPGA芯片的可重构多功能的锁相环时钟发生器。该时钟发生器具有可配置的时钟发生和延时补偿两种模式,分别实现时钟倍频和相位对准的功能。输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。为了提高相位对准和相移的精度,本文设计了一种具有新的快速起振技术的压控振荡器。本文还提出了一种延时分割方法以提高用于实现相移和占空比调节功能的后端分频器的速度。整个时钟发生器使用0.13μm标准CMOS工艺设计制作。测试结果表明,能够实现270MHz到1.5GHz的宽调节范围,当锁定在1GHz时,整个电路功耗为18mW,rms抖动小于9ps,锁定时间为2μs左右。     

锁相环电路中压控振荡器的分析与设计

本文设计了一个应用于高频锁相环（PLL）系统的负阻LC压控振荡器,在传统LC压控振荡器基础上,通过采用二次谐波滤波技术降低了振荡器的相位噪声,并完成了电路的仿真。仿真结果表明,该压控振荡器的振荡频率在1．9—2．1GHz,其频率调节范围达到200MHz,并且在距中心频率1MHz处其相位噪声为-148．825dBc／Hz...     

宽带低相噪分立VCO的设计

压控振荡器(VCO)在通信、雷达、测试仪器等领域中的应用非常广泛,但宽带调谐、低相噪一直是VcO设计的瓶颈.通过对负阻原理的分析,根据三极管的等效电路参数采用准线性法对最佳谐振元件进行了估算,从而提高了对VCO设计的准确性和时效性.由变容二极管对和PC电感组成的并联谐振网络,实现了宽带调谐、低相噪,并对三次谐波分量有所...     

A power scalable PLL frequency synthesizer for high-speed △-∑ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.