A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

Research on optimizing the noise figure of low noise amplifier method via bias and frequency

In this paper,we present the design of an integrated low noise amplifier(LNA)for wireless local area network(WLAN)applications in the 5.15-5.825 GHz range using a SiGe BiCMOS technology.A novel method that can determine both the optimum bias point and the frequency point for achieving the minimum noise figure is put forward.The method can be used to determine the optimum impedance over a relevant wider operating frequency range.The results show that this kind of optimizing method is more suitable for the WLAN circuits design.The LNA gain is optimized and the noise figure(NF)is reduced.This method can also achieve the noise match and power match simultaneously.This proposal is applied on designing a LNA for IEEE 802.11a WLAN.The LNA exhibits a power gain large than 16 dB from 5.15 to 5.825 GHz range.The noise figure is lower than 2 dB.The OIP3 is 8 dBm.Also the LNA is matched to 50 Ω input impedance with 6 mA DC current for differential design.     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

A full W-band low noise amplifier module for millimeter-wave applications

A full W-band Low Noise Amplifier (LNA) Module is designed and fabricated in this letter. A broadband transition is introduced in this module. The proposed transition is designed, optimized based on the results from numerical simulations. The results show that 1 dB bandwidth of the transition ranges from 61 to 117 GHz. For the purpose of verification, two transitions in back-to-back connection are measured. The results show that transmission loss is only about 0.9-1.7dB. This transition is used to interface integrated circuits to waveguide components. The characteristic of the LNA module is measured after assembly. It exhibits a broad bandwidth of 75 to 110 GHz , has a small signal gain above 21 dB. The noise figure is lower than 5dB throughout the entire W-band (below 3 dB from 89 to 95GHz) at a room temperature. The proposed LNA module exhibits potential for millimeter wave applications due to its high small signal gain, low noise, and low dc power consumption     

可重构双频段低噪声放大器的设计和实现

A reconfigurable dual-band LNA is presented. The LNA employs switching capacitors and circuit in to realize the dual-band operation. These methodologies are used to design and implement a reconfigurable LNA for IMT-A and UWB application. The LNA is implemented using TSMC-0.13 μm CMOS technology. Measured performance shows an input matching of better than -13.5 dB, a voltage gain of 18-22.8 dB, with an NF of 4.3-4.7 dB in the band of 3.4-3.6 GHz, and an input matching of better than -9.7 dB, a voltage gain of 14.7-22.4 dB, and with an NF of 3.7-4.9 dB in the band of 4.2-4.8 GHz. According to the measure results, the proposed LNA achieves dual-band operation, and it proves the feasibility of the proposed topology.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

A 0.18 μm CMOS Gilbert low noise mixer with noise cancellation

This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz. The Gilbert mixer is known for its perfect port isolation and bad noise performance. The noise cancellation technique of LNA can be applied here to have a better NF. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz, an average noise figure of 5 dB and a minimum value of 4.3 dB. The core area is 0.6 × 0.45 mm².     

Design of a 24–40 GHz balanced low noise amplifier using Lange couplers

A wide band （24–40 GHz） fully integrated balanced low noise amplifier （LNA） using Lange couplers was designed and fabricated with a 0.15 μm pseudomorphic HEMT （pHEMT） technology. A new method to design a low-loss and high-coupling Lange coupler for wide band application in microwave frequency was also presented. This Lange coupler has a minimum loss of 0.09 dB and a maximum loss of 0.2 dB over the bandwidth from 20 to 45 GHz. The measured results show that the realized four-stage balanced LNA using this Lange coupler exhibites a noise figure （NF） of less than 2.7 dB and the maximum gain of 30 dB; moreover, a noticeably improved reflection performance is achieved. The input VSWR and the output VSWR are respectively less than 1.45 and 1.35 dB across the 24–40 GHz frequency range.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

A △∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.     

Ga2O3缓冲层厚度对柔性衬底沉积Cu/ITO薄膜性能的影响

Cu and Cu/ITO films were prepared on polyethylene terephthalate （PET） substrates with a Ga2O3 buffer layer using radio frequency （RF） and direct current （DC） magnetron sputtering. The effect of Cu layer thickness on the optical and electrical properties of the Cu film deposited on a PET substrate with a Ga2O3 buffer layer was studied, and an appropriate Cu layer thickness of 4.2 nm was obtained. Changes in the optoelectrical properties of Cu（4.2 nm）/ITO（30 nm） films were investigated with respect to the Ga2O3 buffer layer thickness. The optical and electrical properties of the Cu/ITO films were significantly influenced by the thickness of the Ga2O3 buffer layer. A maximum transmission of 86%, sheet resistance of 45 Ω/□ and figure of merit of 3.96 × 10^-3 Ω^ -1 were achieved for Cu（4.2 nm）/ITO（30 nm） films with a Ga2O3 layer thickness of 15 nm.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Synthesis of In2S3 thin films by spray pyrolysis from precursors with different [S]/[In] ratios

Indium sulfide （InzS3） thin films were prepared by chemical spray pyrolysis technique from solutions with different [S]/[In] ratios on glass substrates at a constant temperature of 250 ~C. Thin films were characterized by X-ray diffraction （XRD）, scanning electron microscopy （SEM）, atomic force microscopy （AFM）, energy disper- sive X-ray spectroscopy （EDS）, Raman spectroscopy and optical transmittance spectroscopy. All samples exhibit a polycrystalline structure with a preferential orientation along （0, 0, 12）. A good stoichiometry was attained for all samples. The morphology of thin film surfaces, as seen by SEM, was dense and no cracks or pinholes were ob- served. Raman spectroscopy analysis shows active modes belonging to j3-1naS3 phase. The optical transmittance in the visible range is higher than 60% and the band gap energy slightly increases with the sulfur to indium ratio, attaining a value of 2.63 eV for [S]/[In] ： 4.5.     

氧化铟纳米管的制备及它的甲苯气敏特性研究

Abstract： The pristine In2O3 nanotubes were synthesized by electrospinning and subsequent calcination. Scanning electron microscope, X-ray powder diffraction and transmission electron micrograph were employed to analyze the morphology and crystal structure of the as-synthesized nanotubes. Gas-sensing properties of the as-synthesized In203 nanotubes were investigated by exposing the corresponding sensors to toluene, acetone, ethanol, formalde- hyde, ammonia and carbon monoxide at 340 ℃. The results show that the gas sensor possesses a good selectivity to toluene at 340 ℃. The response of the In2O3 nanotube gas sensor to 40 ppm is about 5.88. The response and recovery times are about 3 s and 17 s, respectively.     

高效太阳电池硅衬底特性对原子层沉积Al2O3薄膜钝化性能的影响

Atom layer deposition （ALD）-Al2O3 thin films are considered effective passivation layers for p-type silicon surfaces. A lower surface recombination rate was obtained through optimizing the deposition parameters. The effects of some of the basic substrate characteristics including material type, bulk resistivity and surface morphology on the passivation performance of ALD-Al2O3 are evaluated in this paper. Surface recombination velocities of 7.8 cm/s and 6.5 cm/s were obtained for p-type and n-type wafers without emitters, respectively. Substrates with bulk resistivity ranging from 1.5 to 4 Ω · cm were all great for such passivation films, and a higher implied Voc of 660 mV on the 3 Ω · cm substrate was achieved. A minority carrier lifetime （MCL） of nearly 10 μs higher was obtained for cells with a polished back surface compared to those with a textured surface, which indicates the necessity of the polishing process for high-efficiency solar cells. For n-type semi-finished solar cells, a lower effective front surface recombination velocity of 31.8 cm/s was acquired, implying the great potential of （ALD）-Al2O3 thin films for high-efficiency n-type solar cells.     

采用Ni/Ti/Ni多层金属在N型4H-SiC衬底改善粘附性和界面的欧姆接触

The Ni/Ti/Ni multilayer ohmic contact properties on a 4H-SiC substrate and improved adhesion with the Ti/Au overlayer have been investigated. The best specific contact resistivity of 3.16 × 10^-5 Ω.cm^2 was obtained at 1050 ℃. Compared with Ni/SiC ohmic contact, the adhesion between Ni/Ti/Ni/SiC and the Ti/Au overlayer was greatly improved and the physical mechanism under this behavior was analyzed by using Raman spectroscopy and X-ray energy dispersive spectroscopy （EDS） measurement. It is shown that a Ti-carbide and Ni-silicide compound exist at the surface and there is no graphitic carbon at the surface of the Ni/Ti/Ni structure by Raman spectroscopy, while a large amount of graphitic carbon appears at the surface of the Ni/SiC structure, which results in its bad adhesion. Moreover, the interface of the Ni/Ti/Ni/SiC is improved compared to the interface of Ni/SiC.     

TiO2 薄膜CMP表面粗糙度的研究

Abstract： Surface roughness by peaks and depressions on the surface of titanium dioxide （TiO2） thin film, which was widely used for an antireflection coating of optical systems, caused the extinction coefficient increase and affected the properties of optical system. Chemical mechanical polishing （CMP） is a very important method for surface smoothing. In this polishing experiment, we used self-formulated weakly alkaline slurry. Other process parameters were working pressure, slurry flow rate, head speed, and platen speed. In order to get the best surface roughness （1.16 A, the scanned area was 10 × 10 μm2） and a higher polishing rate （60.8 nm/min）, the optimal parameters were： pressure, 1 psi; slurry flow rate, 250 mL/min; polishing head speed, 80 rpm; platen speed, 87 rpm.     

不同氧化退火工艺下SiO2/SiC界面特性研究

The effect of the different re-oxidation annealing （ROA） processes on the SiO2/SiC interface charac- teristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 ℃ for 30 min, while a large num- ber of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy （XPS） testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.     

The total dose effects on the 1/f noise of deep submicron CMOS transistors

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI （shallow trench isolation） SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion.