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1.
ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes. 相似文献
2.
多电源和多地的片上ESD保护 总被引:3,自引:0,他引:3
介绍了集成电路设计中的ESD保护的基本原理和几种常用的保护方法并比较其优劣。提出了在多电源、多地时特殊的ESD保护结构(栅耦合结构及共用泄放回路),以及该结构在不同应用中的变化。 相似文献
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This paper describes a design of the electrostatic discharge (ESD) protection device to minimize its area Ap while maintaining the breakdown voltage VESD. Hypothesis tests using measured data were performed to find the severest applied serge condition and to select control factors for the design-of-experiments (DOE). Also, technology CAD (TCAD) was used to estimate VESD. An optimum device structure, where salicide block was employed, was found using statistical methods and TCAD. 相似文献
4.
Ming-Dou Ker Lin K.-H. Chien-Hui Chuang 《Electron Devices, IEEE Transactions on》2004,51(10):1628-1635
A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit. 相似文献
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Haolu Xie Haigang Feng Rouying Zhan Wang A. Rodriguez D. Rice D. 《Electron Device Letters, IEEE》2005,26(2):121-123
Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs. 相似文献
7.
Chang S.J. Chen C.H. Su Y.K. Sheu J.K. Lai W.C. Tsai J.M. Liu C.H. Chen S.C. 《Electron Device Letters, IEEE》2003,24(3):129-131
GaN Schottky diodes were built internally inside the GaN green LEDs by using etching and redeposition techniques. By properly selecting the etching areas underneath the bonding pads, one can minimize the optical loss due to the etching process. Although the reverse current and the forward turn-on voltage were both higher for the GaN LED with a Schottky diode, it was found that the internal Schottky diode could significantly increase the electrostatic discharge threshold from 450 to 1300 V. 相似文献
8.
利用多指条nMOSFET进行抗ESD设计是提高当前CMOS集成电路抗ESD能力的一个重要手段,本文针对国内某集成电路生产线,利用TLP(Transmission Line Pulse)测试系统,测试分析了其nMOSFET单管在ESD作用下的失效机理,计算了单位面积下单管的抗ESD(Electro Static Discharge)能力,得到了为达到一定抗ESD能力而设计的多指条nMOSFET的面积参数,并给出了要达到4000V抗ESD能力时保护管的最小面积,最后通过ESDS试验进行了分析和验证。 相似文献
9.
CMOS集成电路中电源和地之间的ESD保护电路设计 总被引:4,自引:1,他引:3
讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明:在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通.因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。 相似文献
10.
A review on RF ESD protection design 总被引:3,自引:0,他引:3
Wang A.Z.H. Haigang Feng Rouying Zhan Haolu Xie Guang Chen Qiong Wu Guan X. Zhihua Wang Chun Zhang 《Electron Devices, IEEE Transactions on》2005,52(7):1304-1311
Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits. 相似文献
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CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness. 相似文献
13.
An electrothermal diode model intended for implementation in a SPICE-like simulator is presented. The model is valid in the high current, forward-bias and reverse-breakdown regimes where diodes operate during ESD events. We also present a procedure for extracting the temperature of an SOI diode from an I–V measurement. 相似文献
14.
Latchup-free ESD protection design with complementary substrate-triggered SCR devices 总被引:2,自引:0,他引:2
Ming-Dou Ker Kuo-Chun Hsu 《Solid-State Circuits, IEEE Journal of》2003,38(8):1380-1392
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area. 相似文献
15.
Silicon-controlled rectifier (SCR) devices are used as local clamping ESD devices. However, conventional designs suffer from slow turn-on, which causes problems in sub 10 ns charged-device model (CDM) protection, especially in deeply scaled technologies. In this paper, a double-well field-effect diode (DWFED) and an improved field-effect diode (FED) are designed to address this challenge. They are fabricated and characterized in 45 nm silicon-on-insulator (SOI) technology and experimentally demonstrated to be suitable for pad-based local clamping under a normal supply voltage (Vdd) range (at or below 1 V) in high-speed applications. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device performance in CDM events. FED’s advantages in improving transient turn-on behavior and reducing DC leakage current are analyzed and compared with the regular SCR and the DWFED. Technology CAD (TCAD) simulations are used to interpret turn-on behavior and guide design. The improved devices may be implemented in a local clamping scheme that expands the ESD design window for advanced technology nodes. 相似文献
16.
To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (RON * CESD, ICP/CESD, VHBM/CESD, and ICP/ALayout) of ESD protection diodes with new proposed layout styles can be successfully improved. 相似文献
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A new ESD failure mode under inductive IEC stress of automotive Controller Area Network (CAN) bus is identified. Inductor saturation causes increase of the rise-time from 1 ns to ~ 20 ns, leading to non-uniform conduction in the bidirectional ESD protection circuit. A novel mutual ballasting layout technique is introduced to recover the system level ESD performance. 相似文献
19.
Warren R. Anderson 《Microelectronics Reliability》1997,37(7):1087-1103
This paper reviews many of the important issues for building ESD protection with NMOS transistors containing silicided diffusions and lightly doped drain junctions. The impact of device process parameters, such as gate length, side-wall spacer and silicided, graded junctions, on NMOS ESD performance are discussed. More recent process advances, such as LATID and halo implants, are also reviewed. Several varieties of circuits for triggering NMOS protection transistors under ESD conditions are covered. 相似文献
20.
Power-to-failure versus time-to-failure profiles for SOI protection devices are generated through a consideration of Joule heating. Experimental results are presented to justify assumptions made in the investigation of heat flow in SOI devices. A lossy transmission line equivalent model has been used to model the heat diffusion problem. A design space for multifinger NMOS protection devices has been developed on the basis of self-heating constraints. The method of images has been used to transform the multifinger device to an equivalent single-finger device to simplify the heat flow analysis 相似文献