IGBT热疲劳工作对焊料层可靠性的影响

IGBT在实际应用中会频繁处于周期性的高低温循环过程,循环过程中反复作用于IGBT器件的热应力极易在焊料层形成空洞,从而导致器件热阻增大甚至热疲劳失效。通过有限元软件ANSYS建立了两种新的分散空洞模型,在工作功率条件下对比5%到50%中心空洞率及10%到20%分散空洞率模型的热分布并进行模拟分析。结果表明,边缘分散空洞对器件温升影响小于均匀分散空洞和中心空洞,但在温度循环中先于后者出现。空洞率为10%时,边缘分散空洞模型最高温升高了1.6K,与phase11和超声波显微镜实测IGBT器件功率循环5 000次后结果基本一致。     

基于石墨嵌入式结构的SiC功率模块热仿真与优化

SiC器件相比于Si器件,具有更高的功率密度,表现出高的器件结温和热阻。为了提高SiC功率模块的散热能力,提出了一种基于石墨嵌入式叠层DBC的SiC功率模块封装结构,并建立封装体模型。通过ANSYS有限元软件,对石墨层厚度、铜层厚度和导热铜柱直径进行分析,研究各因素对散热性能的影响,并对封装结构进行优化以获得更好的热性能。仿真结果表明,石墨嵌入式封装结构结温为61.675℃,与传统单层DBC封装相比,结温降低19.32%,热阻降低27.05%。各影响因素中石墨层厚度对封装结温和热阻影响最大,其次是铜柱直径和铜层厚度。进一步优化后,结温降低了2.1%,热阻降低了3.4%。此封装结构实现了优异的散热性能,为高导热石墨在功率模块热管理中的应用提供参考。     

焊料层空洞面积对功率器件电阻和热阻的影响

芯片粘贴焊料层是功率器件导热和导电的主要通道,虽然它一般只有几十微米厚,但是却在很大程度上影响着器件的性能和可靠性。采用了高低温冲击的方法对功率器件进行老化,分析器件焊料层空洞面积的改变对器件电热性能的影响。采用超声波扫描(SAM)的方法检测了器件空洞面积的改变量,测试了器件在老化前后的导通电阻和瞬态结到壳的热阻,并进行对比,揭示了功率器件性能退化的机理。实验结果表明,焊料层空洞面积的增加降低了器件导热和导电的能力,器件的导通电阻和热阻随着空洞面积的增加而线性增加。给出了天津环鑫的功率N-MOSFET:50N06的空洞面积的改变(ΔA)与电阻改变(ΔR)和热阻改变(ΔZθjc)的关系。     

基于ANSYS的功率VDMOS器件的热分析及优化设计

针对TO-220 AB封装形式的功率VDMOS器件,运用有限元法建立器件的三维模型,对功率耗散条件下器件的温度场进行热学模拟和分析,研究了基板厚度、粘结层材料及粘结层厚度对器件温度分布的影响.分析结果表明,由芯片至基板的热通路是器件的主要散热途径.基板最佳厚度介于1～1.2 mm之间,且枯结层的导热系数越大、厚度越薄,越有利于器件的散热.     

微系统热阻模型研究及其应用

系统级封装(SIP)实现了高密度、高集成度封装技术,同时散热问题备受关注,热设计中芯片结温预测十分重要.本文采用有限元仿真方法,建立了一种自然对流环境下微系统热阻模型,并通过模型中热阻矩阵预测多芯片总功耗相同条件下的各芯片结温,同时利用热阻测试试验和有限元仿真方法对预测结温进行验证,结果表明热阻矩阵模型预测芯片结温与热阻测试试验和有限元仿真结果误差分别小于2%和5%.但同时发现该热阻矩阵模型的不通用性,对于总功耗变化的多芯片结温,预测结果偏差较大.通过不同总功耗下各热阻矩阵的函数关系建立拟合曲线并修正热阻矩阵模型,修正后的结环境热阻矩阵适用于不同总功率条件、各芯片不同功率条件下的芯片结温预测,预测结果与热阻测试试验中芯片结温和有限元仿真结果误差均小于5%.因此,提出的修正结环境热阻矩阵的方法可以快速且便捷地预测不同功率芯片的结温,并对器件的散热性能进行较为准确的预估.     

IGBT模块超声检测缺陷判据研究

焊层缺陷是影响功率模块寿命和可靠性的主要因素之一,主要采用有限元仿真的研究方法,模拟了焊层缺陷位置、大小等因素对IGBT模块热性能的影响,得到不同的缺陷情况与模块热性能的对应关系并进行拟合,计算出焊层空洞大小临界值,提出了一种IGBT模块超声检测缺陷判据标准。芯片-基板焊层单个空洞率需≤2%,基板-底板焊层单个空洞率需≤2%,芯片-基板焊层整体空洞率与基板-底板焊层整体空洞率之和需≤10%。     

车载IGBT器件封装装片工艺中空洞的失效研究

IGBT芯片在TO-220封装装片时容易形成空洞,焊料层中空洞大小直接影响车载IGBT器件的热阻与散热性能,而这些性能的好坏将直接影响器件的可靠性。文章分析了IGBT器件在TO-220封装装片时所产生的空洞的形成机制,并就IGBT器件TO-220封装模型利用FEA方法建立其热学模型,模拟结果表明:在装片焊料层中空洞含量增加时,热阻会急剧增大而降低IGBT器件的散热性能,IGBT器件温度在单个空洞体积为10%时比没有空洞时高出28.6℃。同时借助工程样品失效分析结果,研究TO-220封装的IGBT器件在经过功率循环后空洞对于IGBT器件性能的影响,最后确立空洞体积单个小于2%,总数小于5%的装片工艺标准。     

温度对压接型IGBT器件内部接触热阻的影响

温度是功率半导体器件备受关注的问题,不仅直接影响功率半导体器件的电气性能,而且还间接影响功率半导体器件的热学和机械特性.压接型IGBT器件内部是电磁场、温度场和结构场的多物理量耦合场,器件内部各组件间的接触热阻是温度场与结构场双向耦合的重要桥梁,也是器件可靠性的重要影响因素.通过单芯片子模组有限元模型分析了各组件间的接触热阻,重点研究了温度对接触热阻的影响,计算了热阻测量前后的接触热阻值,并进行了对比.鉴于目前接触热阻测量方法的局限性,通过测量单个快恢复二极管(FRD)芯片子模组结到壳热阻值与温度的变化关系间接得到接触热阻与温度的关系,并对有限元计算结果进行了验证.     

大功率LED封装界面层裂对界面传热性能的影响分析

对大功率LED封装器件进行了封装界面层裂的热仿真分析,在芯片粘结(DA)层上构建了不同的界面层裂模型,探究了不同层裂形状、位置及分布时界面层裂对芯片热传递的影响规律。结果表明:随着界面层裂面积的增加,LED芯片结温以14℃/mm~2以上的速率增大,层裂面积达到36%时,芯片最高温度为68.68℃,相比无层裂时升高了9.8%;并且界面层裂处于DA层的下界面比上界面对芯片温度分布影响更大;此外,针对同一界面的层裂缺陷,相对于边缘位置和中心位置,封装边角位置的层裂对整体LED封装热传输能力的阻碍作用更明显。     

90 nm PDSOI MOSFET热阻研究

对90 nm PDSOI MOSFET的热阻进行了提取与研究。以H型栅MOSFET为研究对象,将源体二极管作为温度敏感器,通过测量源体结电流与器件温度的关系以及源体结电流与器件功率的关系,获得MOS器件功率与器件温度的关系,从而获取MOS器件热阻值。实验结果表明,该工艺下PMOS器件的热阻比NMOS器件大,其原因是PMOS体区掺杂浓度比NMOS高,而掺杂浓度越高,导热性越差,热阻就越大;H型栅器件的归一化热阻随沟道宽度的增加而增大,其原因是随着沟道宽度的增加,体引出区域对器件导热的贡献变小;热阻随环境温度的上升而减小,其原因是二氧化硅埋氧层的导热率随温度的升高而增大。     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

Thermal and mechanical effects of voids within flip chip soldering in LED packages

This paper investigates the effect of void percentage in the solder layer on the shear strength and thermal property of DA3547 packages by SAC soldering technology. X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages. Furthermore, packages with lower void percentage showed a lower junction temperature based on the results of IR test and finite element simulation. The temperature difference due to the effect void percentage shows a correlation with the input power. For the DA3547 packages studied in this research, voids show limited influence on the junction temperature under 50 mA, the typical current recommended by Cree.     

VDMOS器件贴片工艺中气泡的形成机制与影响

功率MOS管的封装贴片工艺会在贴片层中引入气泡,从而严重降低器件的机械性能、热性能和电学性能.本研究就VDMOS管D-PAK封装模式,给出了贴片工艺中气泡的产生机制及其影响,并利用FEA方法建立了其D-PAK封装的热学模型.根据模拟结果,在贴片层中气泡含量提高时,热阻会急剧增大而降低器件的散热性能.     

Pressure-assisted low-temperature sintering of silver paste as an alternative die-attach solution to solder reflow

Pressure-assisted low-temperature sintering of silver paste is shown to be a viable alternative to solder reflow as a die-attachment solution. A quasihydrostatic pressure is used to lower the sintering temperature. The effect of parameters such as temperature and pressure are investigated. Characterization of the silver-attached samples shows a significant improvement in electrical conductivity, thermal conductivity and mechanical strength of the joint. Given that silver deforms with little accumulation of inelastic strains, and given the absence of large voids in the attachment layer, it is also expected that the joint to be more resistant to fatigue failure than a solder attached junction. Due to the high melting temperature of silver, this alternative process is also suitable for high temperature packages.     

A metallization scheme for junction-down bonding of high-power semiconductor lasers

High-power semiconductor lasers have found increasing applications in industrial, military, commercial, and consumer products. The thermal management of high-power lasers is critical since the junction temperature rise resulting from large heat fluxes strongly affects the device characteristics, such as wavelength, kink power, threshold current and efficiency, and reliability. The epitaxial-side metallization structure has significant impact on the thermal performance of a junction-down bonded high-power semiconductor laser. In this paper, the influence of the epitaxial-side metal (p-metal) on the thermal behavior of a junction-down mounted GaAs-based high-power single-mode laser is studied using finite-element analysis. It is shown that a metallization structure with thick Au layer can significantly reduce the thermal resistance by distributing the heat flow to wider area laterally, and the thermal resistance of a junction-down bonded laser with thick Au metallization is much less sensitive to the voiding in the die attachment solder interface than a laser with thin Au metallization. A metallization structure of Ti-Pt-thick Au-Ti-Cr-Au is designed and implemented, and the metallurgical stability of this metallization scheme is reported. It was found that, without a diffusion barrier, the thick Au layer in the epi-side metallization would be mostly consumed and form intermetallics with the Sn from the AuSn solder during soldering and thermal aging. The Ti-Pt-thick Au-Ti-Cr-Au metallization scheme prevents the diffusion of Sn into the thick Au layer and preserves the integrity of the metallization system. It is a promising candidate for junction-down bonding of high-power semiconductor lasers for improved thermal management and reliability.     

Life prediction of HCPV under thermal cycling test condition

High-concentration photovoltaic (HCPV) module is subject to larger thermal stress due to its more severe temperature fluctuation in real operating conditions. In the thermal cycling test, excessive thermal stress might occur at the peripheral solder layer. For the large area bonding structure, thermal-induced stress is the main cause for cracks. Crack growth is expected to start from the edges of the solder layer and progress to the center. The shrinkage of the bonding area increases the junction temperature of solar cells and reduces the energy-conversion efficiency of the HCPV module. In this study, the stress/strain behavior of the HCPV module under thermal cycling test is analyzed using finite element analysis software, ANSYS®. Results indicate that the von Mises creep strain distribution at the solder layer’s edge is independent of the package’s dimensions. The lifetime of HCPV with uniform solder layer could be predicted by assuming that the crack propagation rate is constant during solder layer degradation. Furthermore, lifetime of tilted HCPV module could be predicted by compensating the variation of thickness of solder layer during crack propagation.     

大功率LED焊料层的可靠性研究

将功率循环方法应用于大功率LED焊料层的可靠性研究,对比分析了在650 mA,675 mA和700 mA电流条件下大功率LED焊料层的热阻退化情况。实验结果表明,循环达到一定次数,大功率LED热阻才开始退化,并呈线性增加,从而引起光通量下降;另外,失效循环次数与电流值之间呈线性关系,并外推出正常工作条件下焊料层寿命为90 968次。对样品进行了超声波检测(C-SAM),发现老化后LED焊料层有空洞形成,这说明空洞是引起热阻升高的主要原因。     

Multilayer diamond heat spreaders for electronic power devices

Single layer diamond and multilayer diamond heat spreader substrates are prepared and bonded to device wafers of silicon and gallium arsenide. Metallization schemes for the diamond surface and the backside of the device wafers are described. Bonding of the device wafers to the diamond substrates using the high thermal conductivity gold–tin eutectic solder is carried out. Characterization of the bond for the distribution of different elements in the metallization layers and the solder, for the presence of microscopic defects such as voids and cracks, for the adhesion strength and for the stability of the bond under thermal cycling is performed. The heat spreader characteristics of the substrates with single and multlayer diamond are determined using infrared imaging of the bonded device wafers and compared with that of wafers bonded to metal substrates. Modeling and analysis of the effectivethermal conductivity showed that the multilayer diamond substrates are better heat spreaders and reduce the device temperature so that the life of the electronic devices is prolonged.     

Effect of process-induced voids on isothermal fatigue resistance of CSP lead-free solder joints

With the progressive miniaturization of electronic devices, process-induced voids in lead-free solder joints affect the assessment of thermal fatigue resistance. Voids appear randomly in a solder joint, making quantitative evaluation of fatigue life difficult. This study examined the effect of process-induced voids on the thermal fatigue resistance of CSP solder joints. CSP specimens were subjected to isothermal mechanical fatigue tests; specifically, the accelerated thermal cycle test. When a void is small, it has no apparent effect on fatigue life. However, when voids having diameters of at least 30% of solder diameter are located along the crack propagation route, fatigue life is shortened. FEA and Miner’s law for estimation of fatigue life suggest that voids affect not only the crack initiation but also crack propagation. Estimated numbers of cycles to failure agree quantitatively with the experimental results. The effects of the size, location, and number of voids can be extracted by FEA. As voids along the crack path become larger, fatigue life decreases. Moreover, when two voids are located near the corner of a solder joint on the crack path, a 30% decrease in life appears. This result agrees with experimental results reported in several literatures.