用VOLTERRA 级数精确分析 MESFET 功率放大器的副谐波负载牵引特性

为了分析CDMA类宽带信号激励下MESFET功放的副谐波负载牵引特性,推导了一组基于MESFET非线性模型的功放电路Volterra转移函数解析式,利用此解析式,建立了三阶交调分量与副谐波负载的解析关系,分析了不同副谐波负载情况下副谐波牵引特性;并推导出了最优副谐波负载的表达式。该文还从两个三阶交调幅度的差异着手,证明了电抗性副谐波负载是造成这一差异的主要因素,上述推导得到的结果与采用ADS软件谐波平衡法仿真得到的结果吻合得很好。     

电容对音频信号总谐波失真和噪声的影响研究

总谐波失真和噪声失真对音频信号质量评估起着举足轻重的作用.首先通过建立基本电路模型理论分析电容对音频信号失真的影响,然后利用仿真工具及实际测试对此理论分析进行验证.结果表明,电容的容值、电压稳定性对音频信号的总谐波失真和噪声有着明显的影响.     

电容对音频信号总谐波失真和噪声的影响研究（李）

总谐波失真和噪声失真对音频信号质量评估起着举足轻重的作用。本文首先通过建立基本电路模型理论分析电容对音频信号失真的影响，然后利用仿真工具及实际测试对此理论分析进行验证，结果证明，电容的容值、电压稳定性对音频信号的总谐波失真和噪声有着明显的影响。     

流水线ADC的行为级仿真

行为级仿真是提高流水线（Pipeline）ADC设计效率的重要手段。建立精确的行为级模型是进行行为级仿真的关键。本文采用基于电路宏模型技术的运算放大器模型,构建了流水线ADC的行为级模型并进行仿真。为验证提出模型的精度,以一个7位流水线ADC为例,分别进行了电路级与行为级的仿真。并做了对比。结果表明这样构建的行为级模型能较好地反映实际电路的特性,同时仿真时间大大缩短。     

太赫兹量子阱探测器的暗电流抑制电路研究

主要研究了太赫兹量子阱探测器读出电路中的暗电流抑制模块。首先从理论上分析了太赫兹量子阱探测器产生暗电流和光电流的原理。由于太赫兹量子阱探测器中电子输运行为非常复杂,难以通过理论推导建立精确等效电路模型的解析表达式。通过对太赫兹量子阱探测器的电流电压实验数据进行拟合,提出压控电流源等效电路模型。利用此模型设计读出电路信号源及暗电流抑制模块,结合读出电路进行仿真验证电路模型的准确性。发现与传统暗电流抑制电路相比,压控电流源电路模型能够在器件工作偏压变化时对其暗电流进行精确抑制,提高读出电路性能,因此更适合作为太赫兹量子阱探测器读出电路的暗电流抑制模块。     

一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

多比特相位量化寄生信号谱分析

对多比特相位量化技术及采样过程进行理论分析，推导出DRFM谐波与交调信号的表达式，进行了计算机仿真试验，分析不同量化位数和不同采样率对信号频谱结构的影响。     

Delta Sigma调制器非理想因素建模

系统构建并研究了开关电容积分器DeltaSigma调制器非理想因素行为级模型.重点实现一种运放非线性直流增益模型,仿真表明它更有效反映奇次谐波失真,为保证模型真实性,综合考虑调制器其他非理想因素,如时钟抖动、量化器失配、采样噪声、开关非线性电阻以及运放参数(色化噪声、饱和电压、增益带宽、摆率等).     

L频段低谐波失真功率放大器的设计

针对L频段低谐波失真功率放大器的设计,进行线性与非线性电路分析仿真和电路的优化设计。从理论上分析了甲乙类功率放大器的谐波失真特性,通过采用具有抑制谐波特性的输出匹配电路以降低功放产生的谐波失真。测试得到电路的关键技术指标为:工作频率范围1 390~1 510MHz,增益35 dB,1 dB压缩点33 dBm,并获得了满意的谐波抑制指标,在1 480 MHz、输出功率33dBm时,二、三次谐波分别为-70 dBc和-63 dBc。结果表明在功放设计中,优化设计输出匹配电路可以有效抑制功放的谐波失真。     

一种高增益低噪声混频器的设计

本文设计了一种高增益低噪声混频器,提出了一种新的吉尔伯特混频器负载级电路.该混频器在3.3V工作电压下,基于Chartered 0.25 μ m标准CM0S工艺设计模型进行仿真验证,优化结果表明,该混频器的增益达到9.02dB,噪声系数为8.88dB,谐波失真降低为-17.29dB.     

A novel low distortion high linearity CMOS bootstrapped switch

This paper proposes a novel low distortion high linearity CMOS bootstrapped switch, and the proposed switch can alleviate the nonlinear distortion of the on-resistance by eliminating first order signal-dependent variation of the overdrive voltage. Based on a 0.18 μm standard CMOS process, the simulation results show that at 100 MHz sampling clock frequency and 49 MHz input signal with 2 Vpp, the proposed switch in differential mode has a Spurious-Free Dynamic Range （SFDR） of 90.1 dB.     

Dual-channel bootstrapped switch for high-speed high-resolution sampling

A novel low-voltage CMOS bootstrapped switch has been designed. In this switch, a PMOS-type bootstrapped circuit combining with an NMOS-type one forms a dual-channel sampling switch that transmits the input signals to the output. Because of this parallel structure, the variation of on-resistance, owing to the variation of the gate overdrive and the threshold voltage, is greatly reduced, exhibiting gain in the sample-and-hold accuracy and linearity. The design was realised in an SMIC 0.18 mum CMOS process and its greatly improved dynamic performance was measured     

一种改进的开关电容Σ-Δ调制器的行为模型

提出了一个开关电容Σ-Δ调制器的行为级模型。该模型不仅考虑了通常非理想特性,包括取样的抖动、kT/C噪声、有限带宽、有限摆率、电荷注入,还考虑了对系统性也有很大影响的开关的非零、非线性导通电阻。提出的模型在Simulink中实现,并与Cadence SPICE的电路级仿真进行了比较验证,二者具有较好的一致性。     

On-state distortion in high electron mobility transistor microwaveand RF switch control circuits

The origin of the distortion generating mechanism in microwave and RF control circuits using high electron-mobility transistors (HEMTs) is presented in this paper. A model is presented for predicting the distortion in series-connected HEMT switches. The theoretical discussion shows that turn-off voltages in the range of 1.0-1.5 V provide the lowest distortion in series switch configurations. A comparison of the HEMT snitch with MESFET switches shows that the HEMT switch generates more distortion than its MESFET counterpart. In addition, the frequency response of HEMT switches is the opposite of the MESFET switch, with less distortion at low frequencies. The model is validated with experimental data taken on a AlGaAs/GaAs HEMT in the series switch configuration     

A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications

A 5-bit lumped CMOS step attenuator with low insertion loss and low phase distortion is designed and simulated in this paper. The proposed attenuator is based on lumped switched bridged-T and π structure attenuators, and implemented with 0.18-μm CMOS technology. Different attenuation states are controlled by NMOS switches. The switches in series branches have channel-shunt resistance to minimize the on-resistance without increasing parasitic capacitance. The NMOS switches in shunt branches are body-floated to improve the power handling performance of the proposed attenuator. Each attenuation module has an inductive phase-compensate low-pass network. The attenuator is controlled with a 5-bit digital signal to achieve the maximum attenuation amplitude range of 0–31 dB with 1 dB increase at 3–22 GHz. The root mean square (RMS) amplitude errors for each one of the 32 states are less than 0.53 dB and the RMS insertion phase is less than 6.3° at 3–22 GHz. The insertion loss is 5.5–13 dB, and the input P_1 dB is 18.4 dBm at 12.5 GHz.     

Polycrystalline cubic silicon carbide photoconductive switch

The first cubic silicon carbide (3C-SiC) photoconductive switches were fabricated from polycrystalline 3C-SiC. The switches had a dark resistivity of 10⁶ Ω/cm. A breakdown field of 250 kV/cm and a peak photocurrent density of 10 kA/cm² through the switch were obtained. The ratio of off-resistance to on-resistance of the switch reached up to 10⁵. The photocurrent had a pulse width as narrow as 15 ns. The trigger gain of the switch was 4.7     

线性变掺杂高阻漂移区LDMOS导通电阻的建模

首先建立了线性变掺杂高阻漂移区LDMOS的导通电阻的模型,通过分析、计算,得出它的导通电阻的解析表达式,然后用MATLAB软件和MEDICI软件对总导通电阻和各部分电阻进行模拟.经过讨论,得出其性能优于均匀掺杂高阻漂移区LDMOS的结论.     

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved.     

具有埋层的大功率集成器件二维简化模型分析

对具有埋层结构的集成大功率器件提出了导通电阻自限制二维模型.在假定条件成立时,推导出器件二维模型导通电阻自限制公式,得出了具有埋层结构的集成大功率器件结构其比导通电阻是随着面积不断增大的结论.通过实验,证实了该结论预测趋势的正确性.该结论对类似集成化大功率器件结构设计具有一定的指导作用.     

Switch Bootstrapping for Precise Sampling Beyond Supply Voltage

Bootstrapped switches are used in a variety of applications including DC–DC converters, pipelined analog-to-digital converters and high voltage switches and drivers. Current work on highly integrated power management applications often requires the ability to measure voltage quantities that exceed the supply voltage in magnitude. This is primarily due to a basic need to maximize efficiency by running the power management IC on as low supply voltage as possible, while still maintaining the ability to sample and measure quantities from the surroundings that could well exceed the battery voltage. In this paper, a new bootstrapped switch is presented. The switch enables the precise sampling of input signals well greater than the chip supply voltage with no static power consumption, and without activating on-chip parasitic body diodes. The bootstrapped switch, presented here, is designed to sample an input signal with a 0–5.5-V range at a supply voltage of 2.75 V. Measurement data shows functionality for a 0–6-V input signal range with a supply voltage as low as 1.2 V.