不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

MOSFET不同厚度薄栅老化中 SILC的机制

通过对栅电流和栅电压漂移的测量 ,证明了均匀 FN应力老化后栅氧化层中陷阱呈非均匀分布 .不同厚度的栅氧化层产生 SIL C的机制不尽相同 ,薄栅以陷阱辅助隧穿为主 ,类 Pool- Frankel机制在厚二氧化硅栅中起主导作用 .     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

MOSFET不同厚度薄栅老化中SILC的机制

通过对栅电流和栅电压漂移的测量，证明了均匀FN应力老化后栅氧化层中陷阱呈非均匀分布．不同厚度的栅氧化层产生SILC的机制不尽相同，薄栅以陷阱辅助隧穿为主，类Pool-Frankel机制在厚二氧化硅栅中起主导作用．     

超薄氧化层中的中性陷阱对隧穿电流的影响和应变诱导漏电流

用数值分析的方法讨论了中性陷阱对超薄场效应晶体管(MOSFET )隧穿电流的影响.中性陷阱引起势垒的变化在二氧化硅的导带中形成一个方形的势阱.对于不同的势垒变化,计算了电子隧穿氧化层厚度为4nm的超薄金属氧化物半导体结构的电流.结果表明,中性陷阱对隧穿电流的影响不能被忽略,中性陷阱的存在使隧穿电流增加,并且通过这个简单的模型能够理解应变诱导漏电流的产生机制.     

一种氮化镓高迁移率晶体管的栅电流噪声模型

This work presents a theoretical and experimental study on the gate current 1/f noise in Al Ga N/Ga N HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of Al Ga N/Ga N HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if Vg Vx, gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the Ga N-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in Al Ga N/Ga N HEMTs.     

Conduction mechanisms in MOS gate dielectric films

This paper reviews the conduction mechanisms in the gate dielectric films of MOSFETs for VLSI and ULSI technologies. They include Fowler–Nordheim tunneling, internal Schottky (or Pool–Frenkel) effect, two-step (or trap-assisted) tunneling, shallow-trap-assisted tunneling, and band-to-band tunneling. The current transport in the gate dielectric films is manly controlled by film material composition, film processing conditions, film thickness, trap energy level and trap density in the films. In general, for a given gate dielectric film, the current transport behaviors are normally governed by one or two conduction mechanisms.     

Trap generation and breakdown processes in very thin gate oxides

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.     

Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

Characterization of leakage current in thin gate oxide subjected to10 keV X-ray irradiation

Two components of the low-field current have been identified in thin oxides, following 10 KeV X-ray irradiation. The first component, observed in the direct tunneling region, can be removed by a 100°C anneal, and is also greatly suppressed if the irradiation is done in vacuum or in a nitrogen ambient, or if the oxide is preannealed before irradiation. The origin of this current is speculated to be related to adsorbed water molecules on the gate surface. The second component is observed to begin in the pre-Fowler-Nordheim tunneling (FNT) region and extends into the FNT region, only in oxides less than ~8 nm thick, and persists even after several days of anneal at 300°C. This current exhibits a power law dependence on radiation dose. The origin of this second component is believed to be due to the trap-assisted tunneling via neutral electron traps, similar to the leakage current observed in the oxide after high-voltage stress     

Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.     

Modeling of Tunnelling Currents in Hf-Based Gate Stacks as a Function of Temperature and Extraction of Material Parameters

In this paper, we show that through electrical characterization and detailed quantum simulations of the capacitance-voltage and current-voltage (I-V) characteristics, it is possible to extract a series of material parameters of alternative gate dielectrics. We have focused on HfO₂ and HfSi_XO_YN_Z gate stacks and have extracted information on the nature of localized states in the dielectric responsible for a trap-assisted tunneling (TAT) current component and for the temperature behavior of the I-V characteristics. Simulations are based on a one-dimensional Poisson-Schroumldinger solver capable to provide the pure tunneling current and TAT component. Energy and capture cross section of traps responsible for TAT current have been extracted     

Edge Effects on Gate Tunneling Current in HEMTs

We elucidate five considerations for accurate estimation of electron tunneling from the gate edges of high-electron mobility transistors (HEMTs). These considerations are listed as follows: 1) edge roughness; 2) net charge at the AlGaN/passivation interface; 3) dielectric constant of the medium above the HEMT surface; 4) nontriangular potential barrier; and 5) negligible angular tunneling from the gate edge. Using these considerations, we calculate the reverse gate current I_G of AlGaN/GaN HEMTs based on thermionic trap-assisted tunneling (TTT) and direct tunneling (DT) mechanisms. These calculations establish that the observed rise in I_G for a gate voltage beyond the threshold is due to tunneling from the gate edges. The calculations also show that the TTT mechanism can predict the measured I_G of AlGaN/GaN HEMTs over a wide range of gate voltages and temperatures and point to the possibility of a rapid rise in I_G at high gate voltages due to the DT mechanism.     

Plasma-induced micro breakdown in small-area MOSFETs

We investigated the impact of latent plasma-induced damage (PID) on the reliability of nMOSFETs with small gate area and gate-oxide thickness of 3.2 nm. To this purpose, we stressed 1500 devices with different antenna areas by using a staircase-like stress voltage and by monitoring the gate leakage at the gate voltage V/sub G/=+2 V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current are characterized by two different oxide-breakdown modes. The first is the well-known hard breakdown (HB), while the second one, which we called micro breakdown (MB), can be modeled as a double trap-assisted tunneling (D-TAT) mechanism and is characterized by a very small leakage current (around 100 pA at the gate voltage V/sub G/=2 V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of microbroken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). Conversely, the hard breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linked to the different generation mechanisms involved in micro breakdown and hard breakdown phenomena.