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设计了一种低压、低功耗、输出阻抗匹配稳定的CMOS差分低噪声放大器.基于源极电感负反馈共源共栅结构,提出了基于MOS管中等反型区最小化Vdd·Id的方法,以优化功耗.在共栅晶体管处并联正反馈电容,以提升电路增益.对电路的噪声系数、输出阻抗稳定性、芯片面积等也进行了优化.仿真结果表明,当电源电压为1V,工作频率为5.8 GHz时,设计的低噪声放大器的噪声系数为1.53 dB,输入回波损耗为-22.4 dB,输出回波损耗为-24.6 dB,功率增益为19.2dB,直流功耗为4.6 mW. 相似文献
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采用ADS软件设计并仿真了一种应用于WiMax2标准的低噪声放大器。该低噪声放大器基于TSMC 0.13μmCMOS工艺,工作带宽为2.3 GHz~2.7GHz。在电路设计中采用噪声抵消技术降低CMOS管的电流噪声。使用共栅极结构进行输入匹配,使用电容进行输出匹配。偏置电路采用电流镜原理。使用ADS2006软件进行设计、优化和仿真。仿真结果显示,在2.3 GHz~2.7GHz带宽内,放大器的电源电压在1.2V时,噪声系数低于1.96dB,增益大于21.8dB,整个电路功耗为9mW。 相似文献
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本文中使用0.13μm CMOS工艺实现了一款应用于脉冲式超宽带无线电的接收机射频前端电路。由于使用了欠采样的接收机架构,接收机中不再具有混频过程。因此,低噪声放大器和可变增益放大器均需要直接处理宽带射频信号。为了优化噪声和线性度,低噪声放大器使用了具有电容交叉耦合的全差分共栅结构,在1.2V电源下仅消耗了1.8mA电流。低噪声放大器之后,一个具有两级结构的电流引导型可变增益放大器被用来实现增益调节功能。同时,低噪声放大器和两级可变增益放大器共同构成了一个三级参差峰化网络,以提高接收机的总体带宽。测试结果表明,该射频前端模块在6-7GHz带宽内实现了5-40dB的增益调节范围,最小噪声系数和最大输入三阶交调分别达到了4.5dB和-11dBm。电路总体功耗为14mW,使用1.2V电源电压,核心部分芯片面积为0.58mm2. 相似文献
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基于0.15μm GaAs E-pHEMT工艺设计并制备了一款0.6~18.0 GHz的低噪声放大器单片微波集成电路。该放大器使用一级共源共栅结构,通过负反馈实现宽带的匹配设计。同时在共栅晶体管栅极增加到地电容,共源管和共栅管漏极增加峰化电感,以提高高频增益,扩展带宽,改善噪声。常温在片测试结果表明,在3.3 V单电源供电下,0.6~18.0 GHz频带内该款低噪声放大器噪声系数典型值1.5 dB,小信号增益约15 dB,增益平坦度小于±0.9 dB,输入、输出电压驻波比典型值分别为1.7和1.8,1 dB压缩点输出功率典型值14 dBm,功耗72.6 mW,芯片面积1.5 mm×1.2 mm。 相似文献
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基于0.18 μm CMOS工艺,设计了一种应用于10 GHz以下无线通信频段的两级超宽带低噪声放大器(LNA)。第一级在互补共源级的基础上通过引入电阻反馈、电感峰化技术和伪电阻结构,在拓展带宽和提高增益的同时降低了噪声。第二级在共源放大的基础上通过电感峰化技术、增益辅助级和缓冲级的使用,提高了电路的增益并改善了输出宽带匹配特性。仿真结果表明,在0.5~9.2 GHz频率范围内,电路增益为14.2±0.2 dB,噪声系数(NF)小于3.97 dB,整体功耗为12.9 mW。 相似文献
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In this paper, the development of 220-GHz low-noise amplifier (LNA) MMICs for use in high-resolution active and passive millimeter-wave imaging systems is presented. The amplifier circuits have been realized using a well-proven 0.1-/spl mu/m gate length and an advanced 0.05-/spl mu/m gate length InAlAs/InGaAs based depletion-type metamorphic high electron mobility transistor technology. Furthermore, coplanar circuit topology in combination with cascode transistors was applied, leading to a compact chip size and an excellent gain performance at high millimeter-wave frequencies. A realized single-stage 0.05-/spl mu/m cascode LNA exhibited a small-signal gain of 10 dB at 222 GHz, while a 0.1-/spl mu/m four-stage amplifier circuit achieved a linear gain of 20 dB at the frequency of operation and more than 10 dB over the bandwidth from 180 to 225 GHz. 相似文献
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这篇文章呈现了一个应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器,使用了改进的带负电容抵消技术Cherry-hooper放大器作为增益单元,采用了新颖的电路技术来实现增益调节,该技术在宽带PGA的设计中具有普适性,并且可以大大简化宽带PGA的设计。PGA通过两级增益单元和一级输出BUFFER的级联获得了最大增益30dB和远宽于3GHz的带宽。该PGA集成进整个60GHz无线收发机里面并且用TSMC65nm的CMOS工艺获得实现。整个接收机前端的测试结果表明接收机前端获得了18dB的可变增益范围和>3GHz的带宽,这证明提出的PGA本身获得了18dB的可变增益范围并且带宽是远大于3GHz的。该PGA电源电压为1.2V,功耗为10.7mW,核心版图面积仅仅为0.025mm^2。 相似文献
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1.9GHz0.18μm CMOS低噪声放大器的设计 总被引:1,自引:1,他引:0
针对1.9GHzPHS和DECT无线接入系统的应用,提出了一种可工作于1.2V电压的基于源级电感负反馈共源共栅结构而改进的CMOS低噪声放大器,并对其电路结构、噪声及线性特性等主要性能进行分析。并与传统的低噪声放大器进行对比,该电路采用两级放大结构,通过加入电容和电感负反馈可以分别实现低功耗约束下的噪声优化和高的线性度。采用TSMC0.18μm CMOS工艺模型设计与验证,实验结果表明:该低噪声放大器能很好满足要求,且具有1.4dB的噪声系数和好的线性度,输入1dB压缩点-7.8dBm,增益11dB,功耗11mW。 相似文献
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Barras D. Ellinger F. Jackel H. Hirt W. 《Microwave and Wireless Components Letters, IEEE》2004,14(10):469-471
A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM. 相似文献
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This paper presents a high-gain wideband low-noise IF amplifier aimed for the ALMA front end system using 90-nm LP CMOS technology.A topology of three optimized cascading stages is proposed to achieve a flat and wideband gain.Incorporating an input inductor and a gate-inductive gain-peaking inductor,the active shunt feedback technique is employed to extend the matching bandwidth and optimize the noise figure.The circuit achieves a flat gain of 30.5 dB with 3 dB bandwidth of 1-16 GHz and a minimum noise figure of 3.76 dB.Under 1.2 V supply voltage,the proposed IF amplifier consumes 42 mW DC power.The chip die including pads takes up 0.53 mm~2,while the active area is only 0.022 mm~2. 相似文献
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An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz. 相似文献
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A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V. 相似文献
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《Microwave Theory and Techniques》2009,57(8):1895-1902
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为了改进传统电路中单端转差分电路的噪声性能,提高传统射频可变增益放大器的覆盖范围和步进精度,该文设计了一种带有低噪声单端转差分电路的射频增益可控放大器。该文利用噪声抵消技术降低了噪声系数,利用电容交叉耦合技术展宽电路带宽,利用输出源级跟随器的增益可调功能实现更高的步进精度。电路采用0.18 mm CMOS工艺,1.8 V供电电源,在170-870 MHz频率信号输入下,可以实现最低3.8 dB的噪声系数,55 dB的动态范围,步进精度0.8 dB,消耗14.76 mW的功耗,面积800 mm×600 mm。测试结果表明在覆盖更宽的频段范围下,该文设计的射频可变增益放大器在消耗相同功率条件下与传统的单端转差分电路相比可以达到更低的噪声系数,同时整个可变增益放大器可以提供更高的步进精度。 相似文献
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In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-mum SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below -12 dB and -10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of -3.55 dBm. The 872 mum times 872 mum DLNA chip consumes 12 mA of current from a 1.8-V DC voltage. 相似文献