A low voltage hybrid bulk/SOI CMOS active pixel image sensor

A hybrid bulk/silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor has been fabricated and studied. The active pixel comprised of reset and source follow transistors on the SOI thin film while the photodiode is fabricated on the SOI handling substrate after removing the buried oxide. The bulk photodiode can be optimized for efficiency with the use of lightly doped SOI substrate without compromising the circuit performance. On the other hand, the elimination of wells on the SOI thin-film allows the use of PMOSFET without increasing the pixel size. The addition of a PMOSFET in the active pixel structure can reduce the minimum operating voltage of the circuit beyond that of conventional designs. With the combination of the high quantum efficiency of bulk photodiode and the low power advantage of SOI technology, the hybrid technology is attractive for scaled low voltage imaging applications     

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.     

Low dark current CMOS image sensor pixel with photodiode structure enclosed by P-well

A low dark current CMOS image sensor pixel which can be easily implemented using a standard CMOS technology without any process modification is presented. Dark current is mainly generated from the interface region between the shallow trench isolation (STI) and the active region. The proposed pixel can reduce dark current by separating the STI region from a photodiode, using a simple layout modification to enclose the photodiode junction with the P-well. A test sensor array has been fabricated using 0.18 mum standard CMOS process and its performance characterised. The dark current of the proposed pixel has been measured as 0.93fA/pixel, which is by a factor of two smaller than that of the conventional design     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

Sensitivity Controllable CMOS Image Sensor Pixel Using Control Gate Overlaid on Photodiode

A new sensitivity controllable pixel structure is proposed for CMOS active-pixel image sensor. The proposed pixel structure has a sensitivity control gate overlaid on the photodiode. The sensitivity of the pixel is controlled by the bias voltage of the control gate that forms a variable accumulation-mode MOS capacitor. The prototype sensor is fabricated with a 0.35-mum CMOS process and consists of 60 times 240 pixels with 5.6-mum pixel pitch. Measurement results show that the sensitivity of the photodiode can be controlled by a factor of 4.     

Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.     

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

A CMOS image sensor with dark-current cancellation and dynamic sensitivity operations

An ultralow dark-signal and high-sensitivity pixel has been developed for an embedded active-pixel CMOS image sensor by using a standard 0.35-/spl mu/m CMOS logic process. To achieve in-pixel dark-current cancellation, we developed a combined photogate/photodiode photon-sensing device with a novel operation scheme. The experimental results demonstrate that the severe dark signal degradation of a CMOS active pixel sensor is reduced more than an order of magnitude. Through varying the bias conditions on the photogate, dynamic sensitivity can be obtained to increase maximum allowable illumination level. Combining the above two operation schemes, the dynamic range of this new cell can be extended by more than 20/spl times/.     

Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

A wide-dynamic-range CMOS image sensor (CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion (FD) of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18 μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second (fps).The proposed CMOS image sensor meets the demands of applications in security surveillance systems.     

Photoresponse analysis and pixel shape optimization for CMOS active pixel sensors

In this work, a semi-analytical model, based on a thorough analysis of experimental data, is developed for photoresponse estimation of a photodiode-based CMOS active pixel sensor (APS). The model covers the substrate diffusion effect together with the influence of the photodiode active-area geometrical shape and size. It describes the pixel response dependence on integration photocarriers and conversion gain and demonstrates that the tradeoff between these two conflicting factors gives an optimum geometry enabling extraction of maximum photoresponse. The parameter dependence on the process and design data and the degree of accuracy for the photoresponse modeling are discussed. Comparison of the derived expression with the measurement results obtained from a 256/spl times/256 CMOS APS image sensor fabricated via HP in a standard 0.5-/spl mu/m CMOS process exhibits excellent agreement. The simplicity and the accuracy of the model make it a suitable candidate for implementation in photoresponse simulation of CMOS photodiode arrays.     

一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

High-sensitivity and no-crosstalk pixel technology for embeddedCMOS image sensor

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-μm CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si₃N₄ film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light     

A 1.9 $e^{-}$ Random Noise CMOS Image Sensor With Active Feedback Operation in Each Pixel

A 1.9 e^- random noise CMOS image sensor has been developed by applying an active feedback operation (AFO), which uses a capacitive feedback effect to floating diffusion (FD) by a gate-source capacitance of a pixel source follower (SF), in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) technology. It is described that the AFO is suitable for CMOS image sensors with LOFIC because the design of the full well capacity and the FD can be independently optimized. The AFO theory is found to be explored to a large signal voltage in detail, as well as the conventional analysis of the capacitive feedback effect of the pixel SF for a small signal voltage. A 1/4-in 5.6- mum-pitch 640(H) times 480(V) pixel sensor chip in a 0.18-mum two-poly-Si three-metal CMOS technology achieves about 1.7 times the sensitivity with AFO compared with the case where the feedback operation is not positively used, resulting in an input-referred conversion gain of 210 muV/e^- and an input-referred noise of 1.9 e^-. A high well capacity of 130 000 e^- is also achieved.     

CMOS有源像素传感器特性分析与优化设计

设计了一个三管有源像素和其用开关电容放大器实现的双采样读出电路.该电路被嵌入一64×64像素阵列CMOS图像传感器,在Chartered公司0.35μm工艺线上成功流片.在8μm×8μm像素尺寸下实现了57%的填充因子.测得可见光响应灵敏度为0.8V/(lux·s),动态范围为50dB.理论分析和实验结果表明随着工艺尺寸缩小,像素尺寸减小会使光响应灵敏度降低.在深亚微米工艺条件下,较深的n阱/p衬底结光电二极管可以提供合理的填充因子和光响应灵敏度.     

SPICE Models of Fluorine-Ion-Irradiated CMOS Devices

CMOS image sensors are attractive for space applications due to their low-power and system-on-chip features. The typical active pixel sensor (APS) is composed of a photodiode and several transistors. Using Fluorine +7 ions with an energy of 17 MeV, the effects of radiation are investigated on photodiodes and transistors manufactured using a standard 0.35-mum CMOS process. Simulation results show that the range of these ions overlaps with the active region of the device. Thus, the proximity effect of the ions on the performance of the device can be important. The tested photodiode showed a leakage current increase after it was irradiated with fluorine ions. The ideality factor of recombination current is observed to increase up to 4. Moreover, an increase in leakage current and absolute threshold voltage was observed in fluorine-ion-irradiated nMOS and pMOS transistors. In this paper, behavioral SPICE models are developed to analyze the contribution of these components to an overall increase in dark current of a CMOS APS.     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

CMOS有源光电传感器像素采集单元成像质量分析

针对CMOS光电二极管型有源像素采集单元中存在的拖影问题,从像素采集单元的工作原理入手,利用光电二极管的等效电路模型,对像素采集单元的光电转换状态和置位状态进行分析.得出造成拖影的根本原因是光电二极管置位后的电压与上一周期末光电二极管的光生电压有关.     

Noise in a CMOS digital pixel sensor

Based on the study of noise performance in CMOS digital pixel sensor(DPS),a mathematical model of noise is established with the pulse-width-modulation(PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator’s reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.     

The effects of deuterium annealing on the reduction of dark currents in the CMOS APS

The effects of low-temperature deuterium annealing on the reduction of dark currents in the CMOS active pixel sensor (APS) have been investigated. Experimental results reveal that deuterium annealing is more effective in reducing dark currents of the CMOS APS than conventional forming gas annealing, because it shows the enhanced passivation efficiency of the interface traps located in the sidewall of the shallow trench isolation. From the characterization results of test structures, it is found that the dark currents generated from the photodiode and floating diffusion node region can be reduced more effectively by using the deuterium annealing process.