FIR数字滤波器在DSP上的实现

在TMS320C54x系统开发环境CCS(Code Composer Studio)下对FIR滤波器的DSP实现原理进行了讨论。利用Matlab中的FIR数字滤波器的函数设计相应的滤波器,对得到的滤波器系数采用Q15格式表示,并用C语言产生模拟输入信号。将获取的系数和输入信号通过相应的指令调到DSP芯片的数据存储器中,运用MAC指令、循环缓冲寄存器、块循环寄存器实现已知混合信号的滤波。通过实验仿真,从输入信号和输出信号的时域和频域曲线可看出在DSP上实现的FIR滤波器能完成预定的滤波任务。     

DSP56200: An algorithm-specific digital signal processor peripheral

Performing finite sums of products is the foundation of digital signal processing (DSP). This paper describes the architecture and two applications of the DSP56200, an algorithm-specific, as opposed to application-specific, digital signal processor peripheral. The DSP56200 implements the finite sum of products and the least mean square (LMS) coefficient update algorithms. Echo cancellation and polyphase sample rate conversion filters are the applications discussed. The requirements of voice-echo cancelers are contrasted with those of data-echo cancelers. Both polyphase interpolators and decimators are described.     

FIR滤波器的DSP实现

介绍了FIR滤波器的基本结构及设计方法,结合实例,给定滤波器的数字指标。利用FDATool来确定FIR滤波器抽头系数。基于DSP平台,采用MATLB产生待滤波输入信号导入到用C语言实现的FIR低通滤波器中,并且在CCS上仿真,对仿真结果与理论值进行比较。波形仿真结果和理论值相吻和表明设计的系统是正确、稳定的。不同的应用场合,FIR滤波器要求有不同性能,只要修改本设计中滤波器的系数,就可以实现性能不同的FIR滤波器。     

A 19.2 GOPS mixed-signal filter with floating-gate adaptation

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.     

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

有限冲击响应数字滤波器的DSP实现

数字滤波是信号处理过程的主要方式,FIR数字滤波器以其系统稳定和易实现线性相位应用更为广泛。设计了采用窗函数法的FIR数字带通滤波器,在DSP中采用单采样模式,在每一个采样周期内只产生一个信号输出值,实时处理采样后的信号。通过MATLAB进行滤波器的仿真,修改滤波器的参数使其达到设计指标。利用窗函数法设立的FIR数字滤波器,是获得较好的主瓣最大能量和旁瓣衰减意义下的最佳设计方法。     

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.     

不同阶数的FIR数字滤波器的DSP实现

在分析了FIR数字滤波器主要特点的基础上，采用最大误差最小化准则的等波纹迫近法，来设计FIR数字滤波器。然后通过Matlab程序设计语言中Remez函数扣Remezord函数计算FIR数字滤波器的系数，并基于美国德州仪器公司生产的TMS320C5402芯片的数字信号处理功能，应用DSP汇编语言编程实现了该滤波器，使不同阶数的FIR数字滤波器都可以用Matlab所得到的结果来修改DSP程序中的数据子程序。     

基于分布式算法的高阶FIR滤波器及其FPGA实现

随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题,提出了一种采用基于位级联的多查找表分布式算法,并以一个32阶8位低通FIR滤波器为例,验证了所提出的方法。仿真结果表明,采用这种方法大大减少了FPGA硬件资源的耗费。     

A Low Power DSP Engine for Wireless Communications

This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wireless digital systems and speech applications. Besides providing a basic instruction set, similar to current day 16-bit DSP's, it contains distinctive architectural features and unique instructions, which make the engine highly efficient for compute-intensive tasks such as vector quantization and Viterbi operations. The datapath contains two Multiply-Accumulate units and one ALU. The external memory bandwidth is kept to two data busses and two corresponding address busses. Still, the internal bus network is designed such that all three units are operating in parallel. This parallelism is reflected in the performance benchmarks. For example, an FIR filter of N taps will take N/2 instruction cycles compared to N for a general purpose 16-bit DSP, and it will require only half the number of memory accesses of a general purpose DSP. This efficiency is reflected in the very low MIPS requirement to implement cellular standards.     

Low power and high-speed implementation of fir filters for software defined radio receivers

The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the intermediate frequency (IF) processing block. Digital filtering is the main task in IF processing. The computational complexity of finite impulse response (FIR) filters used in the IF processing block is dominated by the number of adders (subtracters) employed in the multipliers. This paper presents a method to implement FIR filters for SDR receivers using minimum number of adders. We use an arithmetic scheme, known as pseudo floating-point (PFP) representation to encode the filter coefficients. By employing a span reduction technique, we show that the filter coefficients can be coded using considerably fewer bits than conventional 24-bit and 16-bit fixed-point filters. Simulation results show that the magnitude responses of the filters coded in PFP meet the attenuation requirements of wireless communication standard specifications. The proposed method offers average reductions of 40% in the number of adders and 80% in the number of full adders needed for the coefficient multipliers over conventional FIR filter implementation methods     

应用于ΣΔADC的多级抽取滤波器面积有效实现方法

本文介绍了一种用于音频过采样模数转换器的多级抽取滤波器的面积有效实现方法。抽取滤波器的抽取倍数为256,通带波纹小于0.005dB,阻带抑制达到100dB。通带范围为0-20kHz,输出为48kHz的16比特信号。通过采用含RAM和ROM的面积有效架构,以及对一个运算周期中有效的指令调度,该抽取滤波器在XilinxFPGA上综合后仅使用了不到300个LUT和不到160个Slice。不同于串行或部分串行架构中运算速率通常大于输入采样速率的情况,该实现方法可使得运算速率和采样速率一致,从而简化整体ΣΔADC设计并降低功耗。架构中RAM和ROM的采用使得该抽取滤波器可编程,进一步可改进用于自适应滤波应用。最后,在Modelsim中的RTL仿真结果通过Matlab\Simulink程序进行了验证。     

基于Matlab的FIR带通滤波器设计及DSP实现

借助Matlab的FDATOOL滤波器设计分析软件,设计了一种FIR数字带通滤波器,并对一段含噪语音信号进行滤波。利用汇编语言编程,在DSP上实现了该滤波器。实验结果表明,该数字带通滤波器精确,稳定性好,易于移植,具有很强的实用性与灵活性。     

通信对抗中的自适应滤波技术

自适应滤波是在维纳滤波和Kalman滤波等线性滤波基础上发展起来的一种最佳滤波方法,具有较强的适应性和较优的滤波性能。这里将自适应滤波技术应用于电子对抗领域,利用自适应滤波原理计算出一个数字滤波器,对各信道的增益失配与相移失配进行精确的通道均衡补偿;利用自适应滤波方法设计具有特定频率响应的FIR滤波器,可实现时域宽带波束形成技术,并实现了基于自适应滤波的同平台干扰抵消技术。     

基于DSP6713实现的IIR格型A适应滤波器

区别于普通的FIR,IIR滤波器,为了使滤波器能够按照某种准则自动且较快地达到最佳滤波效果,采用了LMS自适应算法和格型滤波结构相结合的方法。它利用DSP技术在TMS320C6713开发板上构建了验证该音频信号处理算法的硬件平台,并在集成开发环境CCS通过DSP的软件编程完成其工程实现。实验结果表明,该滤波器计算复杂度低,实现速度快,具有良好的实时性和滤波效果。     

Bit-serial VLSI implementation of delayed LMS adaptive FIR filters

The delayed least-mean-square (DLMS) algorithm is useful for adaptive finite impulse response (FIR) filtering applications where high throughput rates are required. In the paper, a bit-serial bit-level systolic array based on new schemes for multiplication and inner-product computation is presented to implement DLMS adaptive N-tap FIR filters. The architecture is highly regular, modular, and thus well-suited to VLSI implementation. It has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N/2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance under proper selection of the step size. Based on a conservative design technique of static complementary metal oxide semiconductor (CMOS) logic, it is shown that the proposed system can be realized in a single chip for most practical applications     

MATLAB-DSP集成环境下的FIR数字滤波器设计

文章介绍了有限冲激响应（FIR）数字滤波器的原理,以及如何根据工程中所给的参数设计所需的FIR数字滤波器。在MATLAB环境下完成FIR数字滤波器的设计与分析,利用CCSIDE完成数字滤波器的实现,通过CCSLink这一高效的工具完成MATLAB与DSP之间的实时数据传送,在不影响DSP运行的情况下完成DSP的开发。利用这一技术可以快速地对DSP进行控制与调试,极大地缩短了DSP的开发周期,提高了DSP的开发效率。     

基于DSP Builder的数字滤波器设计与实现

现场可编程门阵列（FPGA）器件广泛用于数字信号处理领域,而使用VHDL或VerilogHDL语言进行设计比较复杂。提出一种采用FDATOOL工具和DSP Builder实现FIR滤波器的设计方案,按照MATLAB/Simulink/DSP Builder/QuartusII设计流程,使用FDATOOL工具可以实时调整滤波器的参数,采用DSP Builder设计了一个16阶FIR低通滤波器模型,并完成了仿真与验证,将模型转换生成VHDL代码,实现了基于FPGA的数字滤波器的设计。结果表明,该方法简单易行,易修改与移植,可满足设计要求,它验证了采用DSP Builder实现数字滤波器设计的独特优势。     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.     

FIR filters with field-programmable gate arrays

Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail—from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.