2-1-1级联连续时间型ΣΔ调制器系统设计

高阶连续时间型ΣΔ调制器提供了一种有效的获得高分辨率、低功耗模数转换器的方法.提出了一种新型的2-1-1级联的连续时间型ΣΔ调制器结构.采用冲激不变法将离散时间型ΣΔ调制器变换为连续时间型ΣΔ调制器,利用Simulink对该调制器进行系统级建模和仿真,峰值信噪比达到105dB.分析了电路的非理想因素对调制器行为的影响,以获得90dB信噪比为目标确定了电路子模块指标.仿真结果表明,该结构能有效降低系统功耗,并验证了电路的可行性.     

一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

一个应用于数字音频的高性能、低功耗ΣΔ模数转换器

本文介绍了一个应用于18位高端音频的ΣΔ模数转换器(ADC)。它包括一个2-1级联结构的ΣΔ调制器和一个数字抽取滤波器。在系统设计、电路实现和版图设计的过程中采取了许多优化措施,包括：选择了一个能够实现高过载水平的调制器结构并对其系数进行优化,实现了一个高能效的A/AB 类跨导放大器和一个面积和功耗优化的多级抽取滤波器。模数转换器在中芯国际0.18μm 混合信号CMOS 工艺中流片。测试结果表明在22.05 KHz带宽内,信噪失真比和动态范围分别达到91dB和94dB,而芯片面积为2.1 mm2,其中模拟部分仅消耗2.1mA静态电流。     

GNSS射频芯片中小数分频技术研究

针对GNSS射频前端PLL频率综合器中的低杂散小数分频问题,提出了分别基于累加器结构和MASH1-1-1Δ-∑结构的两种小数分频调制器实现方案。进而选取3.996 MHz为GNSS射频前端模拟中频频率,16.368 MHz为PLL频率综合器参考频率,在GPS L1和BD-2 B1频点上对30级累加器级联结构和MASH1-1-1Δ-∑结构的输出功率谱进行分析,并在此基础上对它们的小数杂散特性进行了对比研究。结果表明,MASH1-1-1Δ-∑结构具有噪声整形功能,可将小数杂散由低频段推至高频段,从而在低频段获得更优的杂散特性。由于高频段的杂散可被PLL环路滤波器滤除,故MASH1-1-1Δ-∑结构更适合用在基于PLL的频率综合器中。     

应用于音频芯片的高精度ΣΔ调制器设计

低阶单比特量化ΣΔ调制器简单稳定且特别适用于音频领域的模数转换器。提出了一款应用于音频芯片的二阶单比特量化ΣΔ调制器,利用Simulink对调制器进行建模并确定调制器参数与电路子模块指标。该调制器电路采用CSMC0.35μmCMOS工艺实现,工作的电源电压为5V,采用全差分开关电容技术,功耗为12mW,核心面积为390μm×190μm。在采样频率为12MHz、输入信号频率为20kHz时,调制器精度达到16bit,测试结果验证了设计技术和建模方法。     

一种LFSR加抖的三阶Σ-Δ调制器设计

基于一款小数频率合成器的设计要求,采用三阶MASH1-1-1结构设计了一种全数字三阶Σ-Δ调制器,并针对调制器输出的周期性难以消除的问题,在累加器的进位输入端口进行了LFSR加抖。使用MATLAB对三阶Σ-Δ调制器进行了仿真,结果表明,经过MASH1-1-1三阶Σ-Δ调制器整形后的量化噪声被推到频率高端,环路带宽内基本不存在小数分频产生的量化噪声,从而有效地提高了锁相环的性能。     

基于ΣΔ调制的4 GHz比特流加法器

对传统的基于ΣΔ调制的比特流加法器模型用流水线结构加以改进,使其在高频时可以正常工作。芯片采用源极耦合逻辑进行晶体管级设计,以提高其工作频率。芯片使用TSMC的0.18 μm CMOS 工艺流片,面积为475 μm×570 μm。在FPGA上设计了一个全数字ΣΔ调制器以测试芯片。测试结果表明芯片满足功能和性能的设计要求,芯片可以在高于4 GHz的时钟频率下工作。对比特流加法器的噪声性能用理论和实验结果进行了分析和比较。     

65纳米工艺下低功耗高线性度音频ΣΔ模数转换器的研究与实现

本论文设计了一款适合音频应用的低功耗、高线性度ΣΔADC。此ADC包含了高性能2-1级联单比特量化ΣΔ调制器和采用ROM、RAM设计的低功耗,高面积利用率数字抽取滤波器。此款ADC芯片采用中芯国际65nm 1P8M混合信号CMOS制作工艺,核心面积为0.581平方毫米。测试结果表明,本文设计的ΣΔADC在22.05kHz的音频带宽内,采样频率为5MHz时最高信噪失真比可达90dB,动态范围为93dB,在1.2V供电电压下功耗为2.2mW,同时实现了高性能与低功耗。     

基于锁相环原理的X波段频率源的设计与实现

介绍了一种X波段频率源的设计方法。该文采用2个数字锁相频率合成单环,再环外混频的方法实现了该X波段频率源的设计。该频率源具有相位噪声低,杂散低,频率稳定度高等特点。经试验测试结果表明,该频率源的相位噪声为-94.3dBc@1kHz,-99dBc@10kHz;输出功率大于13dBm,实现了一个性能较好的频率源。     

误差反馈加抖型MASH2-1-2结构Delta-Sigma调制器设计与实现

本文从DSM的线性模型入手,分析了其噪声整形原理,并详细介绍了新型MASH结构的逻辑实现方法.仿真结果表明:与传统或直接加抖型MASH结构相比较,新型MASH结构在谱线连续性及底噪都具明显优势.频率合成应用的实测结果显示:带内杂散优于-75dBc,相位噪声在测试频偏1kHz处可达-96 dBc/Hz.     

Digital extraction of quantization error and its applications to successful design of sigma-delta modulator

A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and cancelled out by adding a digital subtractor and by injecting a purely analog signal from the preceding stage to the next stage. In comparison to conventional MASH modulator structure, analog circuit requirements of the modulator are therefore relaxed, and the number of switched-capacitor digital-to-analog converters and the associated switching energy are lowered. In the absence of extra switching blocks, less flicker and thermal noise would be also injected into the circuit. Different implementations of MASH modulator are presented and analyzed based on the proposed digital quantization error extraction technique. Behavioral-level simulation results prove the mathematical equivalence of the proposed structures with successful MASH designs found in the literature, and confirm the effectiveness of the idea. For a ? 1.4 dB, 19.8 kHz input and an oversampling ratio of 16, a modified 1-V 20-MS/s 2 + 2 MASH modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 78 dB, when the input of the first quantizer is fed to the second stage. The second design based on digital extraction of quantization error achieves a 71 dB SNDR for a ? 8.0 dB, 19.8 kHz input, when the second stage is fed by the output of the first integrator.     

A multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques

This paper presents a new structure for high-resolution, low-power and wideband discrete time multi-stage (DT-MASH) sigma-delta (ΣΔ) modulators. It uses multi-bit digital input feed forward path (DFF) and noise coupling (NC) techniques. With the DFF technique, the modulator does not need a power-consuming analog adder at the quantizer input, and the number of comparators of the quantizer will be reduced significantly. Also, because of the reduced swing of the modulator’s integrators, low power integrators can be used. Using a second-order NC technique with no extra active block, the order of the modulator, which uses some paths between analog stages, is increased, and its performance is improved with zero-optimization of the modulator’s noise transfer function (NTF). Behavioral simulations and extensive mathematical analyses confirm the effectiveness of the proposed structure. The effect of the non-idealities in the DFF and NC paths were considered in the behavioral simulations. To examine its performance, a MASH 2–1 modulator was designed in the circuit level with a 180-nm CMOS technology and 1.8 V power supply. The integrators use a new op-amp switching technique to reduce total power consumption. With an over-sampling ratio (OSR) of 8 for the 10 MHz signal bandwidth, the proposed structure improves the signal-to-noise and distortion ratio (SNDR) by 28 dB compared with a conventional MASH 2–1 structure at approximately the same power consumption and very low complexity.

     

A new sigma-delta modulator architecture for testing using digital stimulus

Sigma-delta modulators are commonly used in high-resolution analog-to-digital converters (ADCs). Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. A new architecture for the modulator is proposed so that its performance can be determined using only digital test stimulus. This architecture does not need analog test stimuli, which is prone to distortion/noise while setting up the high-resolution modulator for testing. Simulation results show that this technique is capable of accurately determining the performance of a second-order sigma-delta modulator ADC.     

A Decorrelating Design-for-Digital-Testability Scheme for $Sigma{-}Delta$ Modulators

This paper presents a novel decorrelating design-for-digital-testability $({rm D}^{3}{rm T})$ scheme for $Sigma{-}Delta$ modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order $Sigma{-}Delta$ modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than $-$5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the ${rm D}^{3}{rm T}$ scheme has the potential to test moderate nonlinearity. The proposed ${rm D}^{3}{rm T}$ scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.      

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections     

A hybrid CT/DT double-sampled SMASH Σ? modulator for broadband applications in 90?nm CMOS technology

In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma?Cdelta (????) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90?nm CMOS technology with 1?V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8?dB and dynamic range of 76.5?dB in 12.5?MHz bandwidth with 17?mW power consumption while operating at 200?MHz sampling rate.     

∑-Δ调制器的六阶噪声整形算法

文章介绍了SDMADC的单一环路和MASH两种结构的优缺点。通过对过采样理论和噪声整形原理的分析,来满足设计的要求推导出六阶MASH算法。为了降低过采样率,同时提高调制器的动态范围和信噪比,可以采用增加积分器的个数,考虑合理的级数,采用三级MASH(2-2-2)结构,采用单比特量化,通过增加调制器的阶数,来满足设计的要求。采用MATLAB进行了仿真,提供一种Sigma-Delta ADC在算法设计中的解决方案。     

Adaptive Correction of Errors in Residue Coupled MASH ΔΣ Modulators

MASH delta-sigma () modulators consist of a cascade of several lower order single-loop modulators. In an ideal cascade, the quantization error from all but the last stage are digitally canceled. The drawback with a cascaded design is the requirement of precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper presents a new, adaptive improvement to the residue coupled MASH delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections. The result is a simple MASH delta-sigma modulator with high precision. Simulations of a 1-1 MASH circuit structure with errors and corrections are included to confirm the theory.     

Reduced Complexity MASH Delta–Sigma Modulator

A reduced complexity digital multi-stage noise shaping (MASH) delta-sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to ldquo1;rdquo shorter words are used in subsequent stages. Experimental results confirm simulations.     

Maximum Sequence Length MASH Digital Delta–Sigma Modulators

This paper presents a modified structure for the first-order digital delta-sigma modulator (DDSM) which yields the maximum sequence length (N) for all constant digital inputs and for all initial conditions. Using this structure, MultistAge noise-SHaping (MASH) DDSMs are developed which, for a constant input, always have a sequence length of N^l regardless of the initial conditions and input value, where N is the sequence length of each stage and l is the number of the first-order stages used in the MASH. The performance is confirmed mathematically, by simulation, and experimentally.