非平行微带线间的串扰抵消研究

非平行微带线是印刷电路板(PCB)上不可避免的互连结构。针对PCB 上非平行微带线间的串扰问题,用平行微带线近似非平行微带线,把平行耦合微带线间的串扰抵消方法应用到非平行耦合微带线中,提出了利用耦合传输线信道传输矩阵方法来进行远端串扰抵消,在对非平行耦合传输线信道传输矩阵进行特征值分解的基础上构建串扰抵消电路。仿真了非平行微带线间夹角分别为q=3°、5°、10°时的串扰,结果表明,该方法可以有效改善非平行微带线上信号眼图的质量,串扰抵消效果良好。     

两相邻耦合RC互连的串扰效应及其抑制

随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。     

IC中多余物缺陷对信号串扰的定量研究

该文研究了铜互连线中的多余物缺陷对两根相邻的互连线间信号的串扰,提出了互连线之间的多余物缺陷和互连线之间的互容、互感模型,用于定量的计算缺陷对串扰的影响。提出了把缺陷部分单独看作一段RLC电路模型,通过提出的模型研究了不同互连线参数条件下的信号串扰,主要研究了铜互连线的远端串扰和近端串扰,论文最后提出了一些改进串扰的建议。实验结果证明该文提出的信号串扰模型可用于实际的电路设计中,能够对设计人员设计满足串扰要求的电路提供指导。     

柔性可延展电路中互连结构设计及布局优化

针对柔性可延展电路由于不合理的互连结构设计和布局而造成的串扰问题,提出一种基于响应面法对柔性可延展电路互连结构进行设计与布局的方法。以柔性可延展电路中的通用互连结构为研究对象,通过正交实验和方差分析,筛选出对串扰存在显著性影响的因素。基于正交设计分析结果,运用中心复合实验设计法获得样本数据,利用ANSYS Electronic Desktop获得串扰响应值,构建串扰与影响因子之间的二阶多项式响应面模型,以近端串扰和远端串扰之和的最小值为优化目标建立优化模型,通过优化算例验证了该方法的可行性,为可延展通用互连导线的优化与布局提供了参考依据。     

高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题.利用高速电路仿真软件HSPICE和MATLAB软件,对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线问的串扰规律,对部分串扰规律进行了探索性的研究.     

平行差分线对间的串扰分析

在高速互连电子设备中,模块之间大多采用差分走线来进行信号传输。然而,不同差分线对之间的串扰会影响到电路性能。本文提出采用多导体传输线理论(MTL)分析差分线对间的串扰,推导了串扰的具体表达式,并结合实际的差分线对模型,将理论分析与CST PCB STUDIO仿真结果进行对比,验证了MTL理论应用于差分线对串扰分析的有效性。     

高速电路PCB中串扰的仿真分析与抑制对策

针对串扰在高速电路印刷电路板(PCB)设计中造成严重的信号完整性问题,介绍一种可尽早发现串扰引起的问题的方法。首先利用信号完整性仿真软件HyperLynx,建立两条攻击线夹一条受害线的三线平行耦合串扰仿真模型;然后通过仿真分析传输线平行耦合长度、平行耦合间距、传输线类型、信号层与地平面层之间的介质厚度等因素对串扰噪声的影响;最后综合这些影响因素,并根据PCB设计顺序,给出抑制串扰的详细措施。实践表明,这些措施对高速PCB的设计,具有实用、可靠和提高设计效率的意义。     

高密度封装中互连结构差分串扰建模与分析

针对传统模型存在较大分析误差的问题,提出高密度封装中互连结构差分串扰建模与分析。在对互连结构差分传输线耦合关系分析的基础上,建立了四线差分结构串扰模型。运用该模型对互连结构差分串扰中的电阻、电容以及电感进行等效分析,解决高密度封装中互连结构差分串扰问题。经试验证明,此次建立模型平均误差为0.042,满足抑制高密度封装中互连结构差分串扰问题的精度需求。     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

IC高密度陶瓷外壳串扰对信号完整性的影响

在高密度陶瓷封装外壳设计中,遇到的包括单信号线的延迟、反射和多信号线间的串扰等噪声问题,以及电源完整性问题,这些问题都严重影响整个电子系统性能的信号完整性。基于高速电路传输线的信号完整性相关基本理论,通过测试和仿真的方法来研究传输线间近端串扰和远端串扰问题。对大规模集成电路外壳CQFP240M进行串扰测试分析,利用仿真软件CST建立微带线和带状线模型,仿真、测试分析相邻传输线间串扰大小的影响因素。根据仿真结果,提出降低串扰的方法,优化设计,提高传输结构性能。     

Altered phase velocity lines for low crosstalk microstrip interconnection of high-speed digital circuits: design and experimental validation

Altered phase velocity lines are a novel kind of parallel microstrip lines for high-speed interconnection of digital circuits, on which the crosstalk is reduced by the different phase velocities of propagation on the adjacent lines. In this paper, a design method is proposed to optimize the geometry sizes of the altered phase velocity lines. The measured results of a prototype altered phase velocity pair designed by the proposed method are presented to validate the design method. And the effects of the process variation are simulated to analyze the robustness of the prototype in fabrication. The altered phase velocity lines outperform the symmetric parallel microstrip lines in terms of the lower far-end crosstalk (FrdCtk) and the lower dielectric loss. This technique reduces the FrdCtk in the pair of the microstrip transmission lines and does not significantly improve the near-end crosstalk. The prototype works at the speed of 2 Gbps for low crosstalk digital signal transmission, while it can transmit the high-speed clock signal at 10.5 GHz, so the altered phase velocity lines are a useful supplementary to the existing low crosstalk interconnection concepts in the scenario that the parallel microstrips have to be placed closely on printed circuit board.     

平行传输线间串扰的仿真及分析

在高速电路设计中,信号完整性问题越来越突出,已经成为高速电路设计师不可避免的问题。该文重点研究了平行传输线间的串扰问题,通过信号完整性分析软件Hyperlynx建立了三线串扰模型并进行仿真分析,最后提出高速PCB设计中减小串扰噪声的策略。     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Twisted differential line structure on high-speed printed circuit boards to reduce crosstalk and radiated emission

Differential signaling has become a popular choice for high-speed digital interconnection schemes on printed circuit boards (PCBs), offering superior immunity to crosstalk and external noise. However, conventional differential lines on PCBs still have unsolved problems, such as crosstalk and radiated emission. When more than two differential pairs run in parallel, a line is coupled to the line adjacent to it because all the lines are parallel in a fixed order. Accordingly, the two lines that constitute a differential pair are subject to the differential-mode crosstalk that cannot be canceled out by virtue of the differential signaling. To overcome this, we propose a twisted differential line (TDL) structure on a high-speed multilayer PCB by using a concept similar to a twisted pair in a cable interconnection. It has been successfully demonstrated by measurement and simulation that the TDL is subject to much lower crosstalk and achieves a 13-dB suppression of radiated emission, even when supporting a 3-Gb/s data rate.     

Computer-aided design of an n-MOS custom IC-“Subscriber Chip” of the 32-lines microprocessor based PAX (private automatic exchange) system

A 40-pin custom IC-“Subscriber Chip” of the subscriber module of the Intel 8085A microprocessor based PAX system (32P₄-32 lines and four parallel conversations) has been designed using CAD techniques. The chip design is based on the LOCOS n-MOS(E-D) process, 8 micron minimum feature size geometries, λ-based design rules and the cell based design approach.DIF-POL contact for the gate-source interconnection of the depletion load transistors has been made with the buried contacts. System routing has been done on two layers: metal and polysilicon/diffusion. Single metal layer has been used for power and ground routing having interdigitated structure.Chip has also been designed for its testability analysis based on the chip partioning approach. Two phases of the testing have been evolved and the test pattern generation sequences got fully integrated with the chip layout.Latest CAD techniques: Applicon AGS/860 VLSI Interactive Graphics Design System, MOS circuit simulation program MSINC and Design Rule Check program (DRC) have been used for the design and chip layout. The entire chip has been laid-out in the area of 3.35 × 3.35 mm² integrating around 500 components including test devices and structures for the evaluation of devices and process parameters. The Electromask pattern generation (PG) tape has been prepared for making chrome masks.A set of eight masks are to be used in the fabrication of the chip and encapsulated in 40 pin LSI package. The subscriber chip makes the PAX system design simple and reliable.     

用半导体激光器和PIN光电探测器设计和实现的光互连链路

本文采用半导体激光器和ＰＩＮ光电探测器,设计和实现了用于计算机ＰＣＩ 一并行经连的光互连链路。在链路的网络接口卡上和实现了激光器的电流源驱动电路以及具有宽动脉的光电探测器放大整形电路,实现了激光器的自动功率保护。通过时分复用技术,实现了ＰＣＩ总线的并行数据在一根光纤中的虚拟并行传输。     

高速数字电路PCB中串扰问题的研究与仿真

针对高速数字电路PCB中传输线间串扰的严重性,从精确分析PCB中串扰噪声的角度出发,在传统的双线耦合模型的基础上,采用了一种三线串扰耦合模型。该模型由两条攻击线和一条受害线组成,两条攻击线位于受害线的两侧,线间采取平行耦合的方式。利用信号完整性仿真软件Hyperlynx对受害线上的近端串扰噪声和远端串扰噪声进行了仿真。仿真结果表明,不同的传输模式和传输线类型、信号层与地平面的距离、耦合长度、传输线间距和信号上升/下降沿等因素会对受害线上的近端串扰和远端串扰产生较大的影响。在分析仿真结果的基础上,总结出了高速PCB设计中抑制串扰的有效措施,对高速数字电路设计有一定的指导意义。     

Investigation of Crosstalk and Coupling Effects of Incident Plane Waves in Orthogonal Microstrips in High-Speed Integrated Circuits Using Full-Wave and Quasi-Static Methods

The crosstalk and coupling of the external fields on orthogonal microstrip transmission lines in different layers have significant effects on signal quality in MMIC and PCBs. In this paper the crosstalk is analyzed in detail using both full-wave and quasi-static methods. The used full wave method is mixed potential integral equation method of moment (MPIEMoM). Because of the weak coupling between lines, the effect of the incident plane-wave is studied by applying transmission line theory in a scattered voltage formulation uses quasi-TEM propagation model for each interconnection and the exact distribution of the incident electric field within the layers. Afterward, by using the predetermined lumped circuit model of the cross-region, the effect of coupling between two lines is calculated and then applied to terminal voltages in 1–20 GHz frequency range which results in the final terminal voltages.     

用于系统级封装的毫米波介质填充波导的研究

基于不断发展的系统级封装技术,提出了一种用于芯片间高速互连的新型可集成的物理器件:硅基毫米波介质填充波导。文中阐述了该器件的物理原理,采用建模、仿真相结合的方法对该模块进行了结构设计,利用新的设计思路结合半导体工艺解决了毫米波互连结构内部的反射、电压驻波比(VSWR)、信号耦合、准TEM-TE-准TEM转换传输问题以及毫米波互连结构阵列中信号泄露的问题,并利用半导体与MEMS加工工艺加以实现。测试结果表明宽度为680μm的单通道矩形波导,-10 d B带宽为9.8 GHz,相对带宽为12.56%;传输损耗为1 d B/cm,工作频带内相邻波导之间串扰低于-40 d B,可以形成大阵列并进行集成,从而实现芯片间数据的并行传输。