高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题.利用高速电路仿真软件HSPICE和MATLAB软件,对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线问的串扰规律,对部分串扰规律进行了探索性的研究.     

若干因素下的高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题。利用高速电路仿真软件HSPICE和MATLAB软件对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线间的串扰规律,对部分串扰规律进行了探索性的研究。     

超深亚微米高速互连的信号串扰研究

探讨了超深亚微米设计中的高速互连线串扰产生机制,提出了一种描述高速互连串扰的电容、电感耦合模型,通过频域变换方法对模型的有效性进行了理论分析。针对0.18μm工艺条件提出了该模型的测试结构,进行了流片和测量。实测结果表明,该模型能够较好地表征超深亚微米电路的高速互连串扰效应,能够定量计算片上互连线间的耦合串扰,给出不同工艺的互连线长度的优化值。     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

两相邻耦合RC互连的串扰效应及其抑制

随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。     

一种新的集成电路互连线串扰模型和估计公式

建立了一个考虑分布电阻,分布电容的互连线混П模型,在这个模型的基础上,分析了终端在最坏条件下的串扰响应,并推导了三阶S域系数的精确表达式,最终,获得了一个新的互连线串扰响应的估计公式,通过与SPICE模拟的结果相比较,该文的模拟结果非常接近实际电路的串扰响应,与相关文献所发表的结果相比较,该模型更符合实际情况,结果也更精确。     

碳纳米材料互连线的单粒子串扰特性研究

碳纳米材料互连线由于其良好的电学、热学和力学特性,成为研究热点.随着技术节点的缩减,串扰效应对电路的影响愈加显著.本文针对单壁碳纳米管束（Single Walled Carbon Nanotube Bundles,SWCNT）、多壁碳纳米管束（Multi Walled Carbon Nanotube Bundles,MWCNT）、单层石墨烯（Single Layer Graphene Nano-Ribbon,SLGNR）及多层石墨烯（Multi Layer Graphene Nano-Ribbon,MGLNR）的互连线,研究了统一的等效RLC模型,并构建了单粒子串扰（SEC）的等效电路,对比分析了四种互连线在32 nm,21 nm和14 nm技术节点下的SEC峰值电压和脉冲宽度.结果表明,与铜互连线相比,碳纳米材料互连线的SEC较弱,但对传输信号的衰减作用较大,综合信号衰减和耦合作用程度,SWCNT和MLGNR更能有效抑制SEC的传播和影响.最后,本文利用灰色理论,分析了SEC与RLC参数之间的潜在关联性.     

互连线间容性串扰对延迟的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是耦合电容的容性串扰,容性串扰引起互连线跳变模式相关的延迟。文中从E lm ore de lay定义的角度推导了互连线受同时跳变的阶跃信号激励时开关因子的大小,分析了互连线受非同时跳变的阶跃信号激励时耦合电容对互连线延迟的影响,给出了不同激励时的受害线延迟计算方法。分析表明,开关因子为0和2不能描述耦合电容对受害线延迟影响的下上限。H sp ice模拟结果证明了分析计算的准确性。     

微米级平行互连线的测试结构设计

研究分析无串扰传输理想模型的条件,根据高速高密度电路板中微米级、亚毫米级互连线电磁串扰特性研究需要,首次提出微米级平行互连线的测试结构设计。经射频电路理论分析推导了测试结构对系统串扰没有影响。构建了有、无测试结构的微米级平行互连线物理模型,仿真分析后,加工制作有测试结构的微米级平行互连线电路板。研究结果表明,当数字基带信号传输频率在0~3 GHz 范围时,无测试结构仿真电路模型、有测试结构仿真电路模型、有测试结构的实验电路板,三者串扰特性吻合;微米级平行互连线的测试结构设计合理,具有工程参 考价值。     

串扰约束下超深亚微米顶层互连线性能的优化设计

优化顶层互连线性能已成为超深亚微米片上系统(SOC)设计的关键.本文提出了适用于多个工艺节点的串扰约束下顶层互连线性能的优化方法.该方法由基于分布RLC连线模型的延迟串扰解析公式所推得.通过HSPICE仿真验证,对当前主流工艺(90nm),此优化方法可令与芯片边长等长的顶层互连线(23.9mm)的延时减小到182ps,数据总线带宽达到1.43 GHz/ μ m,近邻连线峰值串扰电压控制在0.096V_dd左右.通过由本方法所确定的各工艺节点下的截面参数和性能指标,可合理预测未来超深亚微米工艺条件下顶层互连线优化设计的发展趋势.     

高速数字电路PCB中串扰问题的研究与仿真

针对高速数字电路PCB中传输线间串扰的严重性,从精确分析PCB中串扰噪声的角度出发,在传统的双线耦合模型的基础上,采用了一种三线串扰耦合模型。该模型由两条攻击线和一条受害线组成,两条攻击线位于受害线的两侧,线间采取平行耦合的方式。利用信号完整性仿真软件Hyperlynx对受害线上的近端串扰噪声和远端串扰噪声进行了仿真。仿真结果表明,不同的传输模式和传输线类型、信号层与地平面的距离、耦合长度、传输线间距和信号上升/下降沿等因素会对受害线上的近端串扰和远端串扰产生较大的影响。在分析仿真结果的基础上,总结出了高速PCB设计中抑制串扰的有效措施,对高速数字电路设计有一定的指导意义。     

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally.     

超大规模集成电路中互连结构的逻辑模型

本文首次提出一种新观点，超大规模集成电路中互连结构的等效模型应具有层次性，对于底层的电路设计，应将互加看作一种具有分布参数的多端口网络，而对于高层次的模块设计，则应将互连看作一种逻辑元件，基于这种观点，本文提出了一种表格型的逻辑模型，它可以将互连产生的三种主要负效应：串扰、延迟和信号变形人武部考虑在内。     

Design and Characterization of the EBG Waveguide-Based Interconnects

An alternative signal guiding structure, which can be integrated within the printed circuit substrates, is investigated in this paper. The structure is realized by forming a rectangular waveguide in a 2-D electromagnetic bandgap (EBG) substrate. In this manner, a bandpass interconnect is provided that proves to be a promising technology for the high-speed/high-frequency system design. A systematic approach to the design and optimization of this interconnect is presented here followed by investigation of various bend geometries. The studied structures exhibit very low levels of loss and leakage when inspected at tens of gigahertz frequency range. Moreover, the near-end and the far-end crosstalks are monitored in multiple interconnects proving the high efficiency of this alternative routing structure in dense layouts. Nonetheless, the crosstalk performance is degraded as the coplanar microstrip-to-waveguide transitions are added. These transitions are essentially tapered microstrip lines that are connected to other circuitries. Continuous via fences are inserted in the transition sections of multiple structures demonstrating significant improvement in the crosstalk performance.     

Capacitance coupling immune, transient sensitive accelerator forresistive interconnect signals of subquarter micron ULSI

This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

高速数字信号在PCB中的传输特性分析

首先分析了PCB板走线损耗特性,建立分析模型并进行了数值仿真计算,得到了一些有益的结论;然后对PCB走线串扰特性进行了研究,给出了相应的等效电路模型,分析了护卫接地技术中接地孔对串扰抑制的影响.分析结果表明,科学设计护卫接地可以有效地改善PCB走线所引起的串扰,为实现高速数字电路设计打下了基础.     

Crosstalk and transient analyses of high-speed interconnects andpackages

A multiconductor interconnect is modeled using resistors and linear-dependent current and voltage sources. The analysis of a high-speed circuit including lossy interconnection buses is then reduced to simulation of the circuit together with the equivalent circuits of the interconnects. The authors present a new method for the crosstalk and transient analysis of lossy interconnects with arbitrary termination circuits. In order to analyze an interconnect containing N signal conductors, they derive closed-form formulas to determine its transfer functions, and they apply the inverse Fourier transform to obtain its time-domain pulse response functions. Two types of equivalent circuit models can be formulated once the pulse response functions of the interconnect are found. The circuit schematics of the models depend on the number of the signal conductors, irrespective of the physical parameters of the interconnect. These models are compatible with standard circuit simulation tools since they consist of linear resistive networks and linear-dependent sources only. Two example circuits are studied to examine the accuracy and efficiency of the method