一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

混合焦平面最佳性能对R_0A的要求

引言目前,低背景条件下工作的高性能光电红外传感器的发展方向正逐渐趋向于由本征探测器材料和焦平面硅多路调制器组成的混合焦平面器件。在以分立光电二极管探测器/前放结构为基础的焦平面器件中,为达到背景限性能,对探测器的要求极为严格,这往往也就是要求背景散粒噪声远大于热产生暗电流散粒噪声。一些文章所研究的混合IRCCD中的二极管在零偏时达不到背景限性能要求。本文将研究零偏时满足最低背景限性能要求(R_0A要求)的二极管阵列,并研究对二极管的工作特性可能有些什么附加的要求。这些附加要求可能要使二极管在工作状态下的R_0A比零偏R_0A大几个数量级。这类较高的动态阻抗常由对二极管加反偏来实现。这就把对阻抗的要求转变为对漏电流或隧道电流的要求,以使二极管能在足够的反偏范围内满意地工作。     

CMOS有源像素图像传感器的辐照损伤效应

互补金属氧化物半导体(CMOS)有源像素(APS)图像传感器作为光电成像系统的核心器件,被广泛应用在空间辐射或核辐射环境中,辐照损伤是导致其性能退化,甚至功能失效的主要原因之一。阐述了不同辐射粒子或射线辐照损伤诱发CMOS APS图像传感器产生位移效应、总剂量效应和单粒子效应的损伤物理机制。综述和分析了辐照损伤诱发CMOS APS图像传感器暗信号增大、量子效率减小、饱和输出电压减小、噪声增大以及暗信号尖峰和随机电码信号(RTS)产生的实验规律和损伤机理。归纳并提出了CMOS APS图像传感器辐照损伤效应研究亟待解决的问题。     

硅光电二极管的线性度及信噪比分析

通过分析光电检测时硅光电二极管线性响应及噪声特性,给出了硅光电二极管的线性度及信噪比公式,并结合噪声的电流 电压模型,对光电二极管用于光电检测时影响电路信噪比的因素进行了探讨。     

一种高性能X射线CMOS图像传感器的研究

研制了一种采用电流镜积分读出电路和相关双采样电路的X射线CMOS图像传感器(NEW-X-IS),传感器像元由采用CMOS工艺的光电二极管实现,光电二极管产生的光电流通过电流镜放大后在像元外的电容上积分,经相关双采样电路抑制噪声后,由CMOS移位寄存器和多路开关电路输出视频信号.对采用2 μm CMOS工艺研制的64位实验线阵进行参数测试,结果表明NEW-X-IS具有较小的非均匀性、较低的暗噪声、较大的单位面积响应度、较高的输出电压和较宽的动态范围.将其应用于一个实验系统中,得到了不同密度、不同尺寸材料的视频信号波形.     

采用场效应晶体管的低噪声光电探测电路

光电二极管后接结型场效应晶体管的光电探测电路,可提供低频散粒噪声限性能。采用现有的微波场效应晶体管,散粒噪声限性能的频带宽可扩展到兆赫范围。低噪声光电探测器用光电二极管可探测的最小信号功率通常受放大器噪声,而不是光电二极管噪声的限制。不过,在光电二极管后接一个场效应晶体管放大器,可大大改进信噪比。对于临界频率f_c以下的频率,可获得散粒噪声限性能,所以,光电二极管与场效应晶体管组合就成了光电参量上变频器、光电倍增管及低频雪崩光电二极管的劲敌。在下面的讨论中,假定光电二极管接到共源组态的场效应晶体管的栅极上。参照图1,信噪比很容易计算。此图中,反向偏置光电二极管由结电容C_d与串联电阻R_s表     

风云三号黎明星太阳辐照度光谱仪系统噪声与稳定性分析

介绍了搭载在风云三号黎明星上的太阳辐照度光谱仪系统,并对光谱仪可见光通道探测器中的光电倍增管和放大电路产生的噪声进行定量分析.研究表明,在无光照情况下,系统以光电倍增管暗噪声为主;在有光照条件下,系统以阳极散粒噪声为主.基于对噪声的分析,进行地面稳定性试验.采用太阳辐照度光谱仪初样测量丽江2021年10月份的太阳光谱辐...     

长波长PIN／HBT集成光接收机前端噪声分析

文章研究磷化铟(InP)基异质结双极晶体管(HBT)和PIN光电二极管(PIN-PD)单片集成技术,利用器件的小信号等效电路详细计算了长波长PIN/HBT光电子集成电路(OEIC)光接收机前端等效输入噪声电流均方根(RMS)功率谱密度.分析表明:对于高速光电器件,当频率在100 MHz～2 GHz范围内时,基极电流引起的散粒噪声和基极电阻引起的热噪声起主要作用;频率大于5 GHz时,集电极电流引起的散粒噪声和基极电阻引起的热噪声起主要作用.在上述结论的基础上,文章最后讨论了在集成前端设计的过程中减小噪声影响的基本方法.     

CMOS有源像素图像传感器的噪声控制技术

分析了CMOS有源像素图像传感器(APS)的噪声种类及各自产生的原因,介绍了对于不同噪声的噪声控制技术.     

高灵敏度CMOS光电集成接收机设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的CMOS光电集成(OEIC)接收机.具体分析了这个光电集成接收机的噪声和灵敏度及其相互关系.接收机中的噪声主要是电路中电阻的热噪声和MOS器件的闪烁噪声.提出了优化接收机灵敏度的方法.通过低成本的CSMC 0.6μm CMOS工艺流片并对芯片进行了测试.从测试眼图可知,该CMOS光电集成接收机可工作在1.25GB/s的传输速率下,灵敏度为-12dBm.     

Noise in a CMOS digital pixel sensor

Based on the study of noise performance in CMOS digital pixel sensor(DPS),a mathematical model of noise is established with the pulse-width-modulation(PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator’s reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.     

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...     

Low dark current CMOS image sensor pixel with photodiode structure enclosed by P-well

A low dark current CMOS image sensor pixel which can be easily implemented using a standard CMOS technology without any process modification is presented. Dark current is mainly generated from the interface region between the shallow trench isolation (STI) and the active region. The proposed pixel can reduce dark current by separating the STI region from a photodiode, using a simple layout modification to enclose the photodiode junction with the P-well. A test sensor array has been fabricated using 0.18 mum standard CMOS process and its performance characterised. The dark current of the proposed pixel has been measured as 0.93fA/pixel, which is by a factor of two smaller than that of the conventional design     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.     

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease     

High speed SOI CMOS image sensor with pinned photodiode on handle wafer

We have fabricated SOI CMOS active pixel image sensor with pinned photodiode on handle wafer. The structure of one pixel is a four-transistor type active pixel image sensor, which consists of a reset and a source follower transistor on seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on handle wafer. The photodiode could be optimized for better quantum efficiency and low dark currents because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. Most of the wavelengths are absorbed within the visible range, because the optimized photodiode is located on the handle wafer. The response time of SOI CMOS active pixel sensor was about 2 times faster than that of bulk CMOS active pixel image sensor.