Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially Stressed nMOSFETs

We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mum, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is also validated.     

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.      

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler–Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel–Poole emission.      

Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs

On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.      

Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics

Active-area layout dependence of MOSFET parametric characteristics and its reduction by reducing shallow trench isolation (STI)-induced mechanical stress were investigated. Threshold voltages (V/sub th/) and saturation drain currents (I/sub ds/) become sensitive to the active-area layout of MOSFET in scaled-down technology. This phenomenon is the effect of mechanical stress from STI edge, which reduces impurity diffusion in channel region and enhances carrier mobility. To reduce the STI-induced stress, we examined STI-wall-oxide nitridation and STI gap-fill-oxide densifying in pure N/sub 2/ ambient. These processes reduced the reoxidation of the STI wall oxide, therefore reduced the STI-induced stress. According to the new STI process, the active-area layout dependence of V/sub th/ and I/sub ds/ were reduced successfully.     

The Effect of Negative $V_{rm TH}$ of nand Flash Memory Cells on Data Retention Characteristics

We present our study on the dependence of data retention characteristics on the threshold voltage $(V_{rm TH})$ of the cell transistor revealing the combined effect of control gate voltage and cell transistor architecture. Data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler–Nordheim (FN) stress mainly occurs in tunnel oxide away from the region where maximum cell on-current flows. In the sub-50-nm region, due to short distance between the control gate and the shallow-trench isolation (STI) corner, the maximum cell on-current position is shifted from the STI corner to the channel center as control gate voltage decreases. The edge-thin tunnel oxide cell transistor, of which cell on-current flow is separated from tunneling current in negative cell $V_{rm TH}$, shows 0.12-V superior data retention characteristic than the edge-thick tunnel oxide cell transistor at $-$3 V of cell transistor $V_{rm TH}$ in experiment.      

Inversion MOS capacitance extraction for high-leakage dielectricsusing a transmission line equivalent circuit

Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 Å requires correction for the direct tunneling leakage. This work presents a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor. This approach properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance that overcomes discrepancies produced through use of previously reported discrete element based models. An extraction technique is presented to determine the oxide's tunneling and channel resistance of the transmission line equivalent circuit. This model is confirmed by producing consistent C_0x measurements for several different gate lengths with physical silicon dioxide thickness of 9, 12, and 18 Å     

一种新的等离子体边缘损伤的测量方法

在等离子体刻蚀多晶硅工艺中 ,栅边缘氧化层直接暴露在等离子体环境中 ,由于 U V射线的作用栅边缘处将会产生损伤 ,这种损伤包含了大量的界面态和氧化层陷阱 .文中讨论了等离子体边缘损伤与圆片位置关系、天线比之间的关系及它们对器件长期可靠性的影响 ,并使用了低频局部电荷泵技术 .测量的结果包含了损伤产生的快、慢界面态和氧化层陷阱的信息 ,可以较好地测量工艺中产生的栅边缘损伤 ,为评估薄栅 MOSFET的栅边缘损伤提供了一种简单快捷的方法     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

Isolation edge effect depending on gate length of MOSFETs withvarious isolation structures

The gate length (L) dependence of the isolation edge effect is investigated for MOSFETs with various isolation structures. We extract the isolation edge effect for a single L by comparing with an H-shaped gate MOSFET which did not have any influence from the isolation edges. For shallow trench isolation (STI), the isolation edge effect is enhanced for L around the onset of the short channel effect (SCE) and is more prominent for a trench edge with a deeper dip. On the other hand, for the local oxidation of silicon (LOCOS) isolation with an elevated field oxide edge (i.e., the bird's beak), the isolation edge effect operates in the opposite direction against the cases of STI, though it is enhanced around the SCE appearance point. The L dependence is successfully explained using the charge sharing model where the charge shared by the mixing effect between the SCE and the (inverse) narrow width effect [(I)NWE] is introduced at the channel corners. The enhancement of the isolation edge effect results from that the fraction of the charge shared by the mixing effect depends on L. In addition, the difference between STI and LOCOS occurs because the mixing effect for STI is opposite to that for LOCOS     

Effects of Channel Width on Stress Enhancement for Damascene-Gate nFETs With Top-Cut Tensile-Stress Liner

This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length.     

Stress induced leakage current analysis via quantum yieldexperiments

This paper investigates the physical characteristics of stress induced leakage current (SILC) by means of quantum yield (QY) measurements and simulations. QY experiments allow us to infer the energy of tunneling electrons, which is an important factor for the damage generation process. The energy of SILC electrons is analyzed in three different types of p-MOSFET devices: n⁺ gate surface channel and buried channel, and p⁺ gate surface channel. We show that an extra tunneling current component due to native traps can be present even in virgin devices and it is elastic. Then it is shown that SILC electrons have less energy than direct tunneling electrons. This energy loss is then extracted from experimental data and the limitations of this extraction technique are addressed. Finally, experiments on p⁺ gate p-MOSFET clearly demonstrate that electrons tunneling through traps created by electrical stress lose energy irrespective of their initial band. It is then concluded that native and stress induced traps have different physical characteristics     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

For PMOS (p-channel metal–oxide–semiconductor) transistors isolated by shallow trench isolation (STI) technology, reverse narrow width effect (RNWE) was observed for large gate lengths such that the magnitude of the threshold voltage becomes smaller when the channel width decreases. However, PMOS transistors with small gate lengths show up a strong anomalous narrow width effect such that the magnitude of the threshold voltage becomes larger when the channel width decreases. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic transient enhanced diffusion (TED) due to Si interstitials generated by the deep boron source/drain (S/D) implant towards the gate/STI edge.     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

先进工艺下的版图邻近效应研究进展

在28 nm及以下工艺节点,版图邻近效应已经成为一个重要问题。文章概述了版图邻近效应的研究及应用进展,介绍了Poly-gate、High-k/Metal-gate、FinFET等不同工艺下的6种版图邻近效应二级效应,包括阱邻近效应、扩散区长度效应、栅极间距效应、有源区间距效应、NFET/PFET栅极边界邻近效应和栅极线末端效应。在此基础上,详细论述了这些二级效应的工艺背景、物理机理以及对器件电学性能的影响,归纳了目前常见的工艺改进方法。最后,从工艺角度展望了深纳米工艺尺寸下版图邻近效应的发展趋势。     

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.     

Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.     

Modeling study of ultrathin gate oxides using direct tunnelingcurrent and capacitance-voltage measurements in MOS devices

Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.