DC-DC转换器中功率沟槽MOSFET的优化设计

利用工艺和器件模拟软件TSUPREM-4和MEDICI,研究了工艺参数对DC-DC转换器中的功率沟槽MOSFET的通态电阻Ron、栅-漏电容Cgd的影响以及栅-漏电荷Qgd在开关过程中的变化,指出了在设计和工艺上减小通态电阻Ron和栅-漏电容Cgd,提高器件综合性能的途径。     

一种100V分离栅沟槽MOSFET的优化设计北大核心CSCD

把多个侧壁阶梯氧化层应用于分离栅沟槽MOSFET(Split-Gate Trench MOSFET,SGT结构),并把改进的结构称为多阶梯侧壁氧化层分离栅沟槽MOSFET(Multi-Step Sidewall Oxides Split-Gate Trench MOSFET,MSO结构),之后介绍了MSO结构的器件结构和制备工艺,重点借助TCAD仿真软件对MSO结构的外延层掺杂浓度、顶部侧氧厚度与底部侧氧厚度进行优化,最终仿真得到击穿电压为126V,特征导通电阻为30.76mΩ·mm^2和特征栅漏电荷为0.351nC·mm^(-2)的MSO结构.在近似相等的击穿电压下,与传统SGT结构相比,MSO结构的特征导通电阻及特征栅漏电荷均有所降低,这两项参数综合反映器件的优值(FOM=Qgd,sp×RonA)降低了39.6%.     

一种1 200 V碳化硅沟槽MOSFET的新结构设计

为了实现能源的高效利用,通过减小器件的导通电阻和栅漏电容来降低MOSFET的功耗一直是功率电子学的研究热点,但二者存在折衷关系.碳化硅的材料优势使碳化硅MOSFET更适合高频应用,在不过多增大导通电阻的情况下,减小栅漏电容以降低器件在高频应用中的动态功耗是本文的设计重点.提出了一种带有沟槽型源端和N型包裹区的碳化硅沟槽...     

一种电荷平衡结构的沟槽MOSFET的优化设计

为了降低传统沟槽MOSFET的导通电阻和栅漏电容,科研人员提出一种具有电荷平衡结构的SG-RSO MOSFET。在此基础上,利用电荷平衡理论计算出SG-RSO MOSFET结构的主要参数,并借助TCAD仿真软件对外延层厚度及其掺杂浓度、场板氧化层厚度和沟槽深度等主要参数进行合理优化设计。最终,仿真得到击穿电压为92.6 V、特征导通电阻为19.01 mΩ·mm²、特征栅漏电容为1.45 nF·cm-2的SG-RSO MOSFET。该器件性能优于传统沟槽MOSFET。     

低压沟槽功率MOSFET导通电阻的最优化设计

研究了低压沟槽功率MOSFET(<100V)在不同耐压下导通电阻最优化设计的差别。给出了确定不同耐压MOSFET参数的方法,简要分析了沟槽MOSFET的导通电阻;利用Sentaurus软件对器件的电性能进行模拟仿真。理论和仿真结果均表明,耐压高的沟槽MOSFET的导通电阻比耐压低的沟槽MOSFET更接近理想导通电阻,并且,最优导通电阻和最优沟槽宽度随着耐压的提高而逐渐增大。     

一种快速关断沟槽型SOI LDMOS器件

围绕降低沟槽型SOI LDMOS功率器件的优值,提出了一种新型多栅沟槽 SOI LDMOS器件(MG-TMOS)。与常规沟槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不牺牲击穿电压的同时,降低了器件开关切换时充放电的栅漏电荷和器件的比导通电阻。这是因为:1) 新型MG-TMOS器件沟槽里的保护栅将器件的栅漏电容转换为器件的栅源电容和漏源电容,大幅度降低了器件的栅漏电荷;2) 保护栅偏置电压的存在使得器件导通时会在沟槽底部形成一层低阻积累层,从而降低器件的导通电阻。仿真结果表明:该新型沟槽型SOI LDMOS器件的优值从常规器件的503.4 mΩ·nC下降到406.6 mΩ·nC,实现了器件的快速关断。     

用于高效DC/DC变换器的沟槽MOSFET

面对市场对高效率电源的需求,工程师们无不急切期盼快速开关、低rDS(on)的功率MOSFET能有新进展。如今,一种新颖的厚底层氧化物工艺可以让Crss减小为栅极结构器件相应参数的一半,从而大大减少了器件导通所需的栅电荷,缩短了功率MOSFET的开关瞬态过程,同时让导通电阻保持在一个极低的水平上。这一技术对DC/DC变换器来说,意味着电路工作效率将得以提高。     

一种JFET区域具有N型重掺杂的1200 V碳化硅浅槽平面MOSFET器件的设计与优化北大核心

介绍了一种在JFET区域采用浅槽N型重掺杂降低器件比导通电阻与开启损耗的1 200 V碳化硅平面栅MOSFET器件。采用浅槽结构设计，减小了器件栅源电容CGS及栅漏电容与栅源电容比值CGD/CGS,降低了器件的开启损耗。浅槽下方采用的N型重掺杂使得器件反型层沟道压降明显提高，使器件获得了更低的比导通电阻。仿真结果表明，相比于平面栅MOSFET器件，开启损耗降低了20%;相比于平面栅MOSFET与分裂栅MOSFET,器件比导通电阻分别减小了14%和17%。     

30 V UMOS中影响导通电阻平坦度的因素分析

功率MOSFET作为开关器件时,导通电阻的平坦度是衡量其性能的重要参数。研究影响导通电阻平坦度的因素,并对其进行优化,有助于改善器件的性能。低压UMOS中,沟道电阻是导通电阻的主要部分。文章以沟道电阻为分析对象,利用公式分析影响因素,通过Sentaurus TCAD仿真验证了导通电阻平坦度的变化趋势。通过改变P型基区离子注入剂量和栅氧层厚度进行仿真。仿真结果表明,通过减小栅氧层厚度和减少P型基区注入剂量,可获得较好的导通电阻平坦度。     

150 V电荷耦合功率MOSFET的仿真

电荷耦合是适用于中等电压功率MOSFET设计的先进设计理念之一,该设计思想旨在改善器件阻断态下的电场分布从而提高耐压。针对150 V电荷耦合功率MOSFET双外延漂移区(分别为电荷耦合区N1区与非耦合区N2区)电荷匹配问题进行了仿真优化研究,结果表明:N1区和N2区浓度分别约为2.2×1016cm-3和4.5×101 5cm-3时,电场分布更加均匀、耐压更高,且比导通电阻仅为1.306 mΩ·cm2,即击穿电压和比导通电阻间达到最佳匹配。同时,还针对器件不同槽深进行了静态特性和动态特性的整体仿真优化研究,结果表明:槽深在7~9μm时,器件满足耐压要求且击穿电压随双漂移区掺杂浓度匹配程度变化较为平稳。最后,优化结构与传统槽栅MOSFET相比,其栅漏电容和栅电荷大幅降低,器件优值降低了约87%。     

CPU电源电路用沟槽栅MOSFET与e-JFET开关管的功耗对比

本文主要针对低压功率开关管的功耗进行了理论分析，并在此基础上分别对两种典型结构的沟槽栅MOSFET和e—JFET在不同工作频率下的功耗分布和总功耗进行了定量的仿真计算和对比。通过研究发现，在一定工作条件下，常闭型e-JFET比目前常用的沟槽栅型MOSFET仅开关功耗就降低约24％，总功耗则降低约30％。将其运用于CPU电源电路中的开关功率管的制造，在高频领域有着极好的应用前景。     

Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel. By using 2-D numerical simulation, we have shown that by adjusting the lengths of the two gates to allow equal share of the inversion charge by them, we get the optimum device performance. By using $hbox{N}^{+}$ poly-Si as a lower gate material and $hbox{P}^{+}$ poly-Si as an upper gate material, approximately 44% improvement in peak transconductance and 20% improvement in breakdown voltage may be achieved in the new device compared to the conventional trench MOSFET.      

功率MOSFET的研究与进展

器件设计工艺、封装、宽禁带半导体材料和计算机辅助设计4大技术的发展进步使得功率MOSFET的性能指标不断达到新的高度。超级结技术使得高压功率MOSFET的导通电阻大大降低,降低栅极电荷和极间电容的改进沟槽工艺和横向扩散工艺技术进一步提高了低压功率MOSFET的优值因子,中小功率MOSFET继续朝着单片集成智能功率电子发展。功率MOSFET封装呈现出集成模块化、增强散热性和高可靠性的特点。基于宽禁带半导体材料SiC和GaN的功率MOSFET具有高温、高频和低功耗等优异性能,计算机辅助设计工具引领功率MOSFET在工艺设计、制造和电路系统应用方面快速发展。     

Improved performance of trench power MOSFET with SiGeC-based channel

A structure of power trench MOSFET with SiGeC-channel is presented in this paper. The models applicable for the SiGeC-channel trench MOSFET (SGCT) are presented and the improved device characteristics by incorporation smaller-sized carbon atoms substitution into the SiGe system are simulated and analyzed. Simulation results show that SiGeC alloy is a promising channel material for power trench MOSFET application. SGCT owns better I_DS-V_DS characteristic, higher saturated current, lower On-state resistance and bigger breakdown voltage compared to the trench MOSFET devices with SiGe-channel. The stability structure works well and the performance of SGCT is improved by C incorporation though the investigated simulations of On-state resistance and breakdown voltage in different temperatures.     

Lateral power MOSFET for megahertz-frequency, high-density DC/DC converters

DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R/sub DS(ON)/ of 1m/spl Omega/ at a gate voltage of 6V, approximately 50% of the lowest R/sub DS(ON)/ previously reported. The new device has a total gate charge Q/sub g/ of 22nC at 4.5V and a performance figures of merit of less than 30m/spl Omega/-nC, a 3/spl times/ improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in/sup 3/. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.     

一种高速低尖峰电流功率管驱动器电路的设计

利用电荷泵自举原理,提出一种新颖的CMOS驱动电路。该电路在输入信号未进行开关操作时对电容充电,在开关操作发生时,由电荷泵电容和电源一起向负载电容充放电,从而可在不影响充放电时间的前提下降低电源对负载电容的充放电尖峰电流,减小电源噪声。该电路特别适合用来驱动采用高k介质或深槽隔离工艺的功率集成电路,可同时降低上升/下降沿时间和电源尖峰电流,并大幅减小芯片面积。采用中芯国际0.35μm标准CMOS工艺进行流片,测试结果表明,该电路可同时降低负载电容充放电尖峰电流与上升/下降沿时间。     

New Physical Insights on Power MOSFET Switching Losses

Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and efficiency of power electronics circuits. The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach, and subsequently examine the commonly used power loss calculation method in light of the new physical insights. The widely accepted output capacitance loss term is found to be redundant and erroneous based on the new modeling and measurement results. In addition, the existing method of approximating switching times with the power MOSFET gate charge parameters grossly overestimates the switching power loss. This paper recommends a new MOSFET gate charge parameter specification and an effective switching time estimation method to compensate for the power loss calculation error introduced by the two-slope voltage transition waveform of the power MOSFET.      

Investigation of power Trench MOSFETs with retrograde body profile

We present here a power Trench MOSFET (T-MOS) with retrograde body doping profile. The channel length and trench depth are both shortened compared with conventional T-MOS. High energy implantation is used to form retrograde body profile. Electronic parameters of the new structure have been obtained by process and device simulation. The results show that the new structure has much lower specific on-resistance (R_ds,on) because of its shorter channel when compared with conventional T-MOS. As the trench depth is shallowed, the gate charge density Q_g is also reduced.     

Design of 100‐V Super‐Junction Trench Power MOSFET with Low On‐Resistance

Power metal‐oxide semiconductor field‐effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double‐diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on‐state resistance and breakdown voltage. To overcome the tradeoff relationship, a super‐junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on‐state resistance of 1.2 mΩ‐cm² at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.     

迫弹激光引信用脉冲半导体激光电源的设计与应用

设计了适应于迫弹激光近炸引信的小体积、低电压、窄脉宽、高功率的脉冲半导体激光电源.采用电容充放电的模式,选用高速大功率MOSFET管作为开关,设计了相应的高速开关控制电路.激光电源模块的重复频率高达50kHz,常规热电池供电电压条件下的输出脉冲激光峰值功率为9W,光脉冲上升沿为4.2 ns,光脉宽为10 ns,为有效提...