全耗尽SOIMOSFET辐照导致的阈值电压漂移模型

报道了全耗尽SOI MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的加固SOI器件与电路的模拟.讨论了抑制阈值电压漂移的方法.结果表明,对于全耗尽SOI加固工艺,辐照导致的埋氧层(BOX)氧化物电荷对前栅的耦合是影响前栅阈值电压漂移的主要因素,但减薄埋氧层厚度并不能明显提高SOI MOSFET的抗辐照性能.     

An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability

An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform     

一种低功耗抗辐照加固256kb SRAM的设计

设计了一个低功耗抗辐照加固的256kbSRAM。为实现抗辐照加固，采用了双向互锁存储单元（DICE）构以及抗辐照加固版图技术。提出了一种新型的灵敏放大器，采用了一种改进的采用虚拟单元的自定时逻辑来实现低功耗。与采用常规控制电路的SRAM相比，读功耗为原来的11％，读取时间加快19％。     

Rail to rail radiation hardened operational amplifier in standard CMOS technology with standard layout techniques

This work presents a rail-to-rail operational amplifier hardened by design against ionizing radiation at circuit level, using only standard layout techniques. Not changing transistor layout, for instance by using enclosed layout structures, allows design and simulation using the standard models provided by the foundry. The circuit was fabricated on a standard 0.35 μm CMOS process, and submitted to a total ionizing dose (TID) test campaign using a ⁶⁰Co radiation source, at a dose rate of 0.5 rad(Si)/s, reaching a final accumulated dose of 500 krad(Si). The circuit proved to be radiation tolerant for the tested accumulated dose. The design practices used to mitigate TID effects are presented and discussed in detail.     

Single-event multiple transients in guard-ring hardened inverter chains of different layout designs

Single-event multiple transients (SEMTs) measurement based on an on-chip self-triggered method is performed. Measurement results for guard-ring hardened inverter chains of two layout designs, including a source/drain sharing design and a conventional design, are compared under pulsed laser irradiation. Pulsed laser exposures with different energies show that the guard-ring hardened inverter chain with a source/drain sharing design is more sensitive to single-event double transients (SEDTs). It is found that SEDTs with small temporal differences can be merged into single-event single transients (SESTs) thanks to the pulse broadening effect. A layout-hardened design for SEDTs in the guard-ring hardened inverter chain is also suggested.     

基于三模冗余架构的集成电路加固设计

随着科技的发展,人类对太空领域的研究会越来越多,对于航天器件的要求也会越来越高,其中可靠性是航天器件一个重要的指标.空间辐射环境中的高能粒子引发的单粒子翻转事件严重影响星载电子系统的可靠性.现有的抗辐照设计多集中在工艺库和版图的加固上,但是要完全的抑制单粒子故障的产生是不现实的.克服了现有技术中存在的不足,提供了一种基于三模冗余的电路架构,利用冗路架构去屏蔽已发生故障对整个电路的影响,使得整个电路的抗辐照性能得到极大地提升.     

一种新型抗多节点翻转加固锁存器

在纳米锁存器中,由电荷共享效应导致的多节点翻转(MNU)正急剧增加,成为主要的可靠性问题之一。尽管现有的辐射加固锁存器能够对MNU进行较好的容错,但是这些加固锁存器只依赖于传统的冗余技术进行加固,需要非常大的硬件开销。基于辐射翻转机制(瞬态脉冲翻转极性)设计了一种新型抗MNU锁存器。该锁存器可有效减少需保护的节点数(敏感节点数)和晶体管数,因此可减少电路的硬件开销。由于至少存在2个节点可以保存正确的值,因此任何单节点翻转(SNU)和MNU都可以被恢复容错。基于TSMC 65 nm CMOS工艺进行仿真,结果显示,设计的加固锁存器的电路面积、传播延迟和动态功耗分别为19.44μm²,16.96 ps和0.91μW。与现有的辐射加固锁存器相比,设计的锁存器具有较小的硬件开销功耗-延迟-面积乘积(PDAP)值,仅为300.02。     

Circuit layout and yield

The relation between circuit layout and yield is studied. A well-known yield formula is extended to a more general yield formula, in which not necessarily every defect is fatal. A defect sensitivity function is discussed. The function contains, in principle, all information about a chip layout necessary to calculate the yield. The relation between this sensitivity function and the yield formula is explained. If the defect size distribution is known the defect sensitivity function can be used to compute an optimal shrinking factor. An example, in which several defect size distributions are used, shows that these computations are highly sensitive for the form of the defect size distribution     

A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signalflow，complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement，and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.     

信号流驱动的模拟电路版图综合方法

提出了一种新的基于信号流分析的模拟电路版图综合方法.电路分析子系统采用新提出的信号流分析方法再结合已有的电路拓扑分析和电路灵敏性分析方法生成布图约束控制电路性能的衰减.由于考虑了电路中有关信号流的启发式信息,该方法的复杂性较一般的纯粹性能驱动方法小.然后分别在器件生成子系统、布图子系统和布线子系统中实现这些约束,使得这些约束在最容易实现的阶段得到满足.实际的电路例子已经证明了这一方法可以获得出色的电路性能.     

基于RHBD技术的深亚微米抗辐射SRAM电路的研究

研究了目前业内基于抗辐射加固设计(RHBD)技术的静态随机存储器(SRAM)抗辐射加固设计技术,着重探讨了电路级和系统级两种抗辐射加固方式。电路级抗辐射加固方式主要有在存储节点加电容电阻、引入耦合电容、多管存储单元三种抗辐射加固技术;系统级抗辐射加固方式分别是三态冗余(TMR)、一位纠错二位检错(SEC-DED)和二位纠错(DEC)三种纠错方式,并针对各自的优缺点进行分析。通过对相关产品参数的比较,得到采用这些抗辐射加固设计可以使静态随机存储器的软错误率达到1×10-12翻转数/位.天以上,且采用纠检错(EDAC)技术相比其他技术能更有效提高静态随机存储器的抗单粒子辐照性能。     

STI应力效应下的pMOSFET阈值电压物理模型

本文提出了浅沟道隔离（STI）应力效应下的P型MOSFET的阈值电压物理模型,并用不同STI版图位置的130纳米的器件数据进行了验证。基于此STI阈值电压模型,我们对比了p型MOSFET和n型MOSFET在STI应力下的阈值电压和迁移率的变化。数据表明,相比n型MOSFET,p型MOSFET的阈值电压更少地受到STI应力影响,但迁移率却更多地受到STI应力影响。基于此STI阈值电压模型,我们进行了九级震荡环电路的模拟。模拟数据显示,适当的STI应力能使电路平均延迟时间提高约11%,同时也说明了STI应力模型在电路设计中的重要性。     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Modeling and sensitivity analysis of circuit parameters for flip-chip interconnects using neural networks

This paper presents a neural network-based technique for modeling and analyzing the electrical performance of flip-chip transitions. A lumped element model using a simple pi equivalent circuit is used to characterize the electrical properties of the flip-chip bond. Statistical experimental design is used to extract the electrical parameters for flip-chip characterization from measurements and full-wave simulations up to 35 GHz. The extracted data is used to train back-propagation neural networks to obtain an accurate model of the pi equivalent circuit components and s-parameters as a function of layout parameters. The prediction error of the models is less than 5%. The models are used to obtain response surfaces for the entire range of variation of layout parameters. The neural network models are subsequently used to perform sensitivity analysis. All electrical parameters are shown to be sensitive to conductor overlap. The inductance and capacitance of the pi equivalent circuit are sensitive to the bump height. However, the return loss (S₁₁) is insensitive to the change in bump height. The coplanar waveguide width has a significant impact on the s-parameters, as it affects the matching of flip-chip transitions     

体硅集成电路版图抗辐射加固设计技术研究

辐射效应是电路在太空等领域应用时遇到的首要问题,常常会引起电路出错或失效。为了满足抗辐射电路设计的需求,必须提高电路抗辐射效应的能力。文章分析了辐射效应对器件产生的影响。针对电路在辐射环境中应用时存在的问题,文章从版图抗辐射设计加固的角度出发,介绍了抗总剂量的环形栅、倒比例器件,以及抗单粒子昆倾效应抗辐射版图的设计方法。在电路设计时,通过上述几种版图设计方法的应用,可以提高电路的抗辐射性能,进而提高电路的可靠性。     

A physical-based pMOSFETs threshold voltage model including the STI stress effect

The physical threshold voltage model of pMOSFETs under shallow trench isolation(STI) stress has been developed.The model is verified by 130 nm technology layout dependent measurement data.The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET.The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11%improvement of average delay time.This indicates the importance of STI stress consideration in circuit design.     

一款通过抗辐照设计加固技术实现的抗单粒子锁相环

本文设计了一款抗辐照设计加固的锁相环。通过增加一个由锁定探测电路、两个运放和4个MOS器件组成的电荷补偿电路,该锁相环显著地减小了单粒子瞬态引起失锁后系统的恢复时间。许多传统的加固方法主要是致力于提高电荷泵输出结点对单粒子瞬态的免疫力,本文的加固方法不仅能够降低电荷泵输出结点对单粒子瞬态的敏感性,而且也降低了其他模块对单粒子瞬态的敏感性。本文还提出了一种新的描述锁相环对单粒子顺态敏感性的系统模型,基于该模型比较了传统的和加固的锁相环对单粒子瞬态的免疫能力。通过Sentaurus TCAD 仿真平台模拟了单粒子瞬态引起的电流脉冲,用于电路仿真。基于130 nm CMOS 工艺设计了两个锁相环电路,晶体管级的仿真表明本文提出的抗单粒子加固锁相环的恢复时间比传统的锁相环提高了94.3%,同时,电荷补偿电路没有增加系统参数设计的复杂性。     

Layout techniques for radiation hardening of standard CMOS active pixel sensors

This article presents a radiation hardened active pixel sensor implemented in a standard 0.35 μm CMOS process. The integrated circuit is composed of a 64 × 64 pixel matrix with a 25 μm pixel pitch and has four different pixel architectures. There are also test structures to permit the characterization of the MOS transistors. The radiation hardening of the circuit is implemented with two layout techniques: enclosed geometry transistors and guard rings. It is shown that, with these techniques, the sensor is able to operate with total ionization doses that surpass 500 krad, which is more than double of the requirement for our application. Also, the techniques do not compromise the optical response of the pixels. To obtain an electrical model of the designed transistors, an EKV MOSFET Model was extracted.     

Layout analysis as supporting tool for failure localization: Basic principles and case studies

To be able to localize a defect on results obtained by failure analysis tools like emission microscopy or OBIRCH analysis it is necessary to understand the effect of a certain defect on an integrated circuit, as only some defects can directly be pinpointed by these analysis methods. In the majority of cases, only second order effects are visible, e.g., a floating gate will cause a transistor to emit light. In that case, the failure site differs from the point of emission.While the physical principles of common defects are well understood one has also to consider the layout of an integrated circuit. By matching the failure analysis results obtained by emission microscopy or OBIRCH analysis to the layout and schematics of a failing device it is possible estimate the root cause of the failure. Thus, the failure site can be narrowed down, to be finally able to proceed with the physical analysis for root cause determination.This paper will give an overview of physical failures that can occur and their effects on emission and OBIRCH analysis. These failure modes will then be correlated to the layout of a device in order to be able to estimate the root cause of a failure based on analysis techniques like emission microscopy and OBIRCH analysis. Finally, we will present case studies of successful failure localization based on layout analysis.