共查询到19条相似文献,搜索用时 93 毫秒
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超薄栅MOS结构恒压应力下的直接隧穿弛豫谱 总被引:1,自引:1,他引:0
随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 . 相似文献
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随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具. 相似文献
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针对AlGaN/GaN HEMT器件在寿命试验过程中经常出现的栅源、栅漏和源漏泄漏电流随试验时间的延长而增大的现象,展开了深入的研究.分析了当前HEMT器件泄漏电流的各种主流退化模型,通过试验发现热载流子效应、逆压电效应等难以完全解释泄漏电流间的退化差异.进一步的研究显示,电极间的泄漏电流的差异主要是由材料中的缺陷和陷阱的密度分布不均匀造成的.在应力的作用下,初始密度越大,试验过程中缺陷和陷阱的增长速度就越快,泄漏电流的增长速度也就越快.但应力撤除后,由陷阱辅助隧穿导致的泄露电流会逐渐地得到恢复. 相似文献
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Rodriguez R. Miranda E. Pau R. Sune J. Nafria M. Aymerich X. 《Electron Device Letters, IEEE》2000,21(5):251-253
The degradation of ultrathin oxides subjected to constant-current stresses is analyzed using two independent procedures. First, the injected charge to breakdown is estimated from the stress-induced leakage current (SILC) evolution during the stress. Second, the degradation that leads to the breakdown is directly measured using a two-step stress test. The evolution of the SILC during constant-current stresses proceeds at a rate that decreases with time. Moreover, under low current density stress conditions the normalized SILC at breakdown is no longer constant. However, our two-step test methodology shows that the degradation of the oxide evolves roughly linearly until the breakdown. These apparently contradictory results can be reconciled assuming that the degradation at breakdown is independent of the stress conditions and using the initial SILC generation rate to calculate the charge-to-breakdown by linear extrapolation. The implications for the use of SILC data as a degradation monitor are discussed 相似文献
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The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress. 相似文献
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R. Rodríguez E. Miranda R. Pau J. Su M. Nafría X. Aymerich 《Microelectronics Reliability》2000,40(4-5)
The normalized stress induced leakage current (SILC) measured when the oxide is subjected to low level constant-current stresses shows a tendency towards saturation at large charge fluences. To investigate the origin of this saturation, the degradation of the oxide has been analyzed using two independent methods: SILC data analysis and a two-step stress test. The results show that, although under low stress currents the SILC saturation is observed, the degradation (i.e., the generation of defects) proceeds until the soft breakdown (SBD) event takes place. The implications for the use of SILC data as degradation monitor are analyzed. 相似文献
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G. Ghidini C. Capolupo G. Giusto A. Sebastiani B. Stragliati M. Vitali 《Microelectronics Reliability》2005,45(9-11):1337
A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness limited by the higher gate leakage current (Stress Induced Leakage Current, SILC) after cycling. It is possible to reduce the oxide degradation during cycling by reducing the stress pulse duration and increase the time between pulses. This allows the annealing of precursor sites with an overall reduction of stable traps. Aim of this work is the investigation of the SILC induced by pulsed stress and the corresponding charge trapped in the oxide during stress. The impact of the oxidation technology will also be discussed. 相似文献
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Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented. 相似文献
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Schwalke U. Gschwandtner A. Innertsberger G. Kerber M. 《Electron Device Letters, IEEE》1999,20(7):363-365
We have realized direct-tunneling (DT) gate oxide (1.6 nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a corner parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel-doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench corner parasitics are eliminated by the advanced process architecture without increasing process complexity. Fully functional direct-tunneling oxide MOSFET's with excellent electrical characteristics confirm the feasibility of this novel approach 相似文献
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The reversibility of charge buildup and SILC generation in thin oxides subjected to successive stress/anneal cycles is investigated. It is demonstrated that in thin oxides both electron trapping and SILC are nearly fully reversible degradation processes having a generation kinetics almost unchanged after several stressing/annealing cycles. The annealing kinetics of the SILC is likely associated to the out diffusion of charged defects (possibly trapped holes or H+) whose characteristics (diffusivity, activation energy) are independent of the oxide thickness. Moreover correlation between electron trapping and SILC generation has been studied. 相似文献
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In the present work we study reliability issues of Pt/HfO2/Dy2O3/n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge (Qinj) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics. 相似文献
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de Blauwe J. van Heudt J. Wellekens D. Groeseneken G. Maes H.E. 《Electron Devices, IEEE Transactions on》1998,45(8):1745-1750
In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO2 gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism 相似文献