A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R² is 0.99 and verify the effect of duty cycle compensation.     

数字控制高频Boost变换器设计与实现

在数字控制高频开关电源中,数字补偿控制器及高分辨率数字脉宽调制( DPWM)是系统实现的关键.这里以Boost变换器为例,基于电路平均法建立了变换器的数学模型,采用单变量系统极点配置法设计了数字补偿控制器.为了在不提高系统时钟频率的情况下提高系统精度,提出一种数字时钟管理器与数字抖动相结合的新型混合DPWM方法,提高了...     

高精度逆变电源输出电压直流漂移的调偏控制

逆变器中的隔离环节、各功率器件等存在漂移和特性不对称以及正弦脉宽调制(sinusoidal pulse width modulation,SPWM)都会引起逆变电源输出电压的直流漂移。该文提出了一种高精度逆变电源输出电压直流漂移的调偏控制方案,系统采用基于现场可编程门阵列(field programmable gate array,FPGA)的全数字控制。给出了直流调偏控制的基本原理及其闭环控制系统。分析了模数转换器(analogue-to-digital converters,ADC)精度与数字脉宽调制(digital PWM,DPWM)精度之间的关系,并给出了抑制极限环振荡的必要条件。提出一种提高DPWM精度的新方法,可以进一步提高直流调偏控制的精度。最后,在一台单相8重化9电平电压型逆变器的实验平台上进行实验验证,实验结果表明了该控制方案的有效性。     

Direct torque control of induction motor based on advanced discontinuous PWM algorithm for reduced current ripple

In recent years several discontinuous pulse width modulation (DPWM) methods are reported to improve the performance of AC drives at high modulation indices. It is proved that the performance of the popular PWM methods is modulation index dependent and no single DPWM method provides satisfactory performance over the entire high modulation range. Two popular existing DPWM methods renowned with the names DPWMMIN, DPWMMAX clamp each phase for 120° duration in every cycle of its fundamental voltage. It is observed that only the zero state is different in these two sequences. In this paper, it is proposed that, utilizing these two DPWM sequences and by changing the zero state at any spatial angle γ, where γ is between 0° and 60°, an infinite number of DPWM sequences including the existing DPWM methods and advanced DPWM (ADPWM) methods can be generated which are categorized as “continual clamping” and “split clamping” sequences. Using these ADPWM techniques an optimal split clamping sequence-based DTC of induction motor is proposed. With the proposed DTC method it is shown that steady state line current distortion at higher line side voltages is reduced significantly compared with the CDTC as well as conventional SVPWM (CSVPWM)-based DTC.     

一种TSPWM调制算法的等效实现方式

针对传统三相逆变器中由于高频开关动作而产生高峰值高频共模电压的问题。首先对电机驱动系统空间矢量脉宽调制(SVPWM)与三态脉宽调制(TSPWM)下的共模电压进行对比分析,并在此基础上研究了非连续脉宽调制(DPWM1)的调制波与TSPWM的调制波之间的关系,给出了基于载波的TSPWM调制实现方法。然后,研究了正负极性载波之间的关系,给出了负极性载波在工程上的一种实现方式。最后对所提的TSPWM调制实现方法进行仿真和试验验证。结果表明,可以用DPWM1的调制波的实现方式来实现TSPWM的调制波,负极性载波下的脉宽调制(PWM)信号可以由正极性载波代替生成。     

改进的中点钳位型三电平逆变器非连续脉宽调制策略

为了降低开关损耗,非连续脉宽调制(DPWM)方法被广泛应用于中点钳位型三电平逆变器(NPC-TLI),但是DPWM在中点电压的控制上表现了某些不足。为了减少NPC-TLI的开关损耗并同时控制中点电压,文中采用切换钳位模式来实现对中点电压的有效控制。为了避免在切换钳位模式时引入附加开关动作,提出了一种可实现钳位模式无缝切换的改进的脉宽序列的DPWM策略。通过仿真和实验,对所提策略、传统DPWM和现有优化DPWM算法进行了比较。理论分析和实验结果均表明,所提策略具有良好的中点电压控制能力以及开关损耗降低能力。     

一种高分辨率数字时间鉴别器设计

在雷达自动距离跟踪与宽带成像雷达系统中,高分辨率数字时间鉴别器是关键部件,它将跟踪的目标信号相对跟踪波门之间的延迟时间差转换成相应的距离误差。介绍了一种高分辨率数字时间鉴别器的实现过程并给出了仿真结果,为了获得高精度时间分辨率,采用模拟插值技术设计了t/D变换器,代替传统的时钟脉冲计数器对时间延时差的测量,经测试,其测时误差小于200ps,抖动误差小于53ps。     

高分辨THz-TDS采集传输的嵌入式设计与优化

为了满足太赫兹高分辨检测及实时处理需求,利用光电导天线产生和探测太赫兹时域光谱信号,基于现场可编程门阵列(field programmable gate array, FPGA)实现太赫兹时域光谱的采集、维纳滤波反卷积处理、传输和上位机显示等功能。将采集到的太赫兹时域光谱数据进行维纳滤波反卷积处理,实现还原太赫兹信号、提高时间分辨率以及降噪的效果,将数据由以太网传输的方式传输到上位机进行实时显示,针对实际检测中太赫兹信号反卷积后脉宽较宽,提出在维纳滤波反卷积算法中引入与频率相关的函数对算法进行优化,使信号的脉宽变窄,提高检测精度。优化的维纳滤波反卷积算法处理结果相比于原始算法信噪比增加7 dB,脉宽降低0.2 ps,实现更高的检测分辨能力,算法在FPGA中实现,精度误差小于0.7%,处理效率提升14.29倍,并且减少后期上位机处理时间。     

数字控制高频变换器的新颖PWM方法

数字化PWM调制在高频应用中存在精度受限制的问题。该文提出一种新的PWM技术－双调制PWM,结合高频和低频的优势,解决了数字化PWM中高频与精度之间的矛盾,使数字化PWM可用于高频,高精度电能变换器之中,理论分析,仿真和实验结果均论证了这一方法的优越性。     

一种考虑中点平衡的ANPC变换器的混合断续脉冲宽度调制策略

对于ANPC(active neutral-point-clamped)变换器,采用断续脉冲宽度调制DPWM(discontinuous pulse width modulation)具有开关损耗小的优点,但也存在中点电位波动较大的问题,为此提出了一种基于切换钳位的混合断续脉冲宽度调制Hybrid DPWM策略,实现D...     

Novel current‐source multilevel inverter driven by single gate drive power supply

This paper proposes a novel current‐source multilevel inverter, which is based on a current‐source half‐bridge topology. Multilevel inverters are effective for reducing harmonic distortion in the output voltage and the output current. However, the multilevel inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but the pulse width of the output PWM waveform is limited. Furthermore, high‐speed power switching devices are indispensable to create a high‐frequency power converter, but various problems, such as high‐frequency noise, arise due to the high dv/dt rate, especially in high‐side switching devices. The proposed current‐source multilevel inverter is composed of a common emitter topology for all switching devices. Therefore, it is possible to operate it with a single power supply for the gate drive circuit, which allows stabilizing the potential level of all the drive circuits. In this paper, the effectiveness of the proposed circuit is verified through experimental results. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(2): 88–95, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20475     

Actively mode-locked strained-InGaAsP multiquantum-well lasersintegrated with electroabsorption modulators and distributed Braggreflectors

This paper describes picosecond pulse generation at 20 Gb/s by monolithic mode-locked lasers integrated with electroabsorption modulators and distributed Bragg reflectors. The electroabsorption modulator using strained-InGaAsP multiquantum wells acts as a pulse shortening gate when a sinusoidal voltage is driven at a large reverse bias voltage. To obtain transform-limited picosecond pulses, the required spectral bandwidth of the distributed Bragg reflector is estimated. Pulse generation around 4 ps with a time-bandwidth product of 0.5 has been performed at a repetition rate of 20 GHz. Driving conditions of the modulator, such as bias voltage and modulation frequency, are investigated. It is shown that an increase in the intensity noise is the main factor limiting performance     

基于I-DPWM的三电平中点钳位光伏逆变器漏电流抑制方法

对于三电平中点钳位光伏逆变器,基于断续脉宽调制(discontinuous pulse width modulation, DPWM)并通过选择特定矢量进行钳位控制的方法,存在矢量分解计算时间长、注入共模电压分量和漏电流过大等不足。对此,提出了一种基于I-DPWM的三电平中点钳位光伏逆变器漏电流抑制方法。通过计算各类DPWM等效调制波来解析注入的低频共模电压分量。针对低频共模电压分量最小的DPWM1,在低频共模电压不连续点注入新的零序分量,通过减小低频共模电压来抑制漏电流幅值。同时,采用载波实现DPWM,免去了复杂的矢量运算。最后,在Matlab/Simulink平台建立了20 kW三电平中点钳位光伏逆变器的仿真模型,同时结合所设计的125 W实验样机验证了所提方法的有效性。     

Compact CMOS active quenching/recharge circuit for SPAD arrays

Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time‐of‐flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single‐photon avalanche diode (SPAD) detectors. Active quenching and recharge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold‐off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 µm complementary metal‐oxide‐semiconductor (CMOS) technology. The SPAD has a quasi‐circular shape of 12 µm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon‐detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break‐down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post‐layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse‐width jitter is below 1.8 ns when dead time is set to 40 ns. Copyright © 2015 John Wiley & Sons, Ltd.     

基于FPGA的新型混合DPWM方法及其实现

数字脉宽调制器DPWM(Digital Pulse Width Modulation)是数字控制开关电源的核心。一般在DPWM的实现中,存在DPWM分辨率与系统工作频率之间的矛盾。本文提出了一种新型混合高分辨率DPWM的实现方法,该方法利用FPGA中数字时钟管理DCM(Digital Clock Manager)的倍频及移相功能、高频计数比较模块及数字“抖动”方法,在系统硬件工作频率为32MHz,开关频率为1MHz的条件下,实现了11位的DPWM分辨率。文中论述了各模块的原理及实现方法,并给出了基于Virtex-II FPGA的仿真和实验结果。     

风电变流器改进型断续脉宽调制策略

大功率风力发电变流器中,存在开关损耗和电流总谐波失真THD(total harmonic distortion)难以均衡的矛盾。如何优化调制方式,以提高系统效率,减小电流谐波,是大功率风电变流系统的核心技术之一。针对风电变流器宽频率、宽电压运行范围的特点,分析直驱风电变流器采用断续脉宽调制策略下的损耗和谐波性能,发现不同工况下主要关注指标不同,轻载时电能质量恶劣、开关损耗低,而重载时开关损耗严重、电能质量好;但是常用调制方式很难兼顾。为解决该问题,提出一种适用于永磁同步机直驱风电变流器的新型断续脉宽调制策略,该调制策略对开关损耗和THD的优化特性随变流器工作范围变化,实现不同工况下主要关注指标的优化。最后通过实验平台验证了该方案在重载时减小开关损耗,在轻载时降低电流谐波的有效性。     

Ultrafast all‐optical switching using pulse trapping by ultrashort soliton pulse in birefringent optical fiber

Ultrafast all‐optical switching by use of pulse trapping in birefringent optical fiber is demonstrated both experimentally and numerically. The wavelengths of the control soliton pulse and the trapped soliton pulse are shifted to satisfy the condition of group velocity matching. Furthermore, the energy of the trapped pulse is increased through Raman gain of the control pulse. Only a signal pulse in the pulse train with temporal separation of about 1.2 ps is successfully picked off. The repetition frequency corresponds to 0.83 THz. The spectrogram of the optical switching is directly observed using the X‐FROG technique. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 158(3): 38–44, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20470     

A new parallel ZVS converter with less power switches and low current stress components

A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse‐width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse‐width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

Pulse generation for soliton systems using lithium niobatemodulators

We describe the principle of operation and performance of several soliton pulse sources and also a complete soliton transmitter based on lithium niobate modulators. Subsystems based on lithium niobate modulators are attractive because the modulators are now commercially available, qualified for system use, can operate up to very high speeds, and can operate over a wide wavelength range. The pulse sources we describe are based on two techniques. The first is the chirped pulse compression technique in which one or two sinusoidally driven modulators generate frequency chirped pulses that are subsequently compressed to the desired width using dispersion in a fiber. In the second technique, sinusoidally driven modulators are cascaded serially to form pulses. Using these techniques we produced nearly transform-limited pulses at repetition rates up to 15 GHz with a FWHM pulsewidths from 10-33% of the pulse period. A complete soliton transmitter using a single modulator to simultaneously generate optical pulses and encode data is also discussed. The performance of this compact transmitter in a 2.5-Gb/s soliton system experiment is comparable to other more common soliton transmitters