Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Analytical model and characterization of abnormally structured MOSFETs

Electrical characteristics of abnormally structured n-MOSFETs having uncontacted active regions are experimentally investigated using test devices with various gate widths. Linear resistance and saturation drain current of the devices are estimated by a simple schematic model, which consists of parallel-connected conventional devices having parasitic resistors. A comparison of experimental results of conventional and abnormal devices gives the parasitic resistance caused by abnormal active structure. The increment rate of the parasitic resistance depending on gate width shows two categories, which are logarithmic increment at narrow device and exponential increment at wider device. The performance degradation in the wider device is also explained by the reduction of effective channel area. The suggested model provides a physical analysis of the abnormal transistor and shows good agreement with the measured drain current in linear and saturation regions for both forward- and reverse-modes.     

横向电阻区对IGBT过电流关断能力的影响研究

针对绝缘栅双极晶体管(IGBT)在过电流关断测试中被烧毁的问题,设计了三种不同的横向电阻区结构。为了分析器件的失效机理,研究不同结构横向电阻区对过电流关断能力的影响,借助Sentaurus TCAD仿真工具构建了器件模型,模拟了器件的整个过电流关断过程。对三种结构器件在过电流关断过程中的内部关键物理参量的变化情况进行分析,发现不同长度的横向电阻区对空穴的抽取效率不同,进而可以影响到电流密度分布。当电阻区增加到一定长度时,可以有效提升过电流关断能力,避免器件烧毁失效。     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

电流增益截止频率为236GHz的InAIN/GaN高频HEMT

研制了高电流增益截止频率(fT)的InAlN/GaN高电子迁移率晶体管(HEMT).采用金属有机化学气相沉积(MOCVD)再生长n+GaN非合金欧姆接触工艺将器件源漏间距缩小至600 nm,降低了源、漏寄生电阻,有利于改善器件的寄生效应;使用低压化学气相沉积(LPCVD)生长SiN作为栅下介质,降低了InAlN/GaN HEMT栅漏电;利用电子束光刻实现了栅长为50 nm的T型栅.此外,还讨论了寄生效应对器件fT的影响.测试结果表明,器件的栅漏电为3.8 μA/mm,饱和电流密度为2.5 A/mm,fT达到236 GHz.延时分析表明,器件的寄生延时为0.13 ps,在总延时中所占的比例为19％,优于合金欧姆接触工艺的结果.     

Overview and status of metal S/D Schottky-barrier MOSFET technology

In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.     

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system     

The effect of high fields on MOS device and circuit performance

A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.     

SOI-LIGBT寄生晶体管电流增益的研究

采用二维器件模拟仿真软件Tsuprem4和Medici模拟了SOI-LIGBT的n型缓冲层掺杂剂量、阳极p+阱区长度、漂移区长度以及阳极所加电压对SOI-LIGBT寄生晶体管电流增益β的影响,通过理论分析定性的解释了产生上述现象的原因和机理,并且通过实验测试结果进一步验证了分析结论的正确性。其中,n型缓冲层掺杂剂量对电流增益β的影响最为明显,漂移区长度的影响最弱。基本完成了对SOI-LIGBT寄生晶体管电流增益β主要工艺影响因素的定性分析,对于SOI-LIGBT的设计有一定的借鉴意义。     

A new lateral MOS-controlled thyristor

A lateral MOS-controlled thyristor (LMCT) structure that uses an MOS gate to turn it both on and off is presented. The device structure offers improved maximum turn-off current capability and forward voltage drop. The former is achieved by using a DMOS transistor and a parasitic vertical p-n-p transistor, while the latter is achieved by eliminating a parasitic lateral p-n-p transistor in the conventional structure. The device utilizes the resurf technique to achieve high area efficiency, breakdown voltage, and reliability. Devices that have more than 250-V forward blocking capability were fabricated in dielectrically isolated silicon tubs using the standard bipolar-CMOS-DMOS process     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Analysis of negative differential resistance in theI-V characteristics of shorted-anode LIGBT's

The physical mechanism responsible for the negative differential resistance (NDR) in the current-voltage characteristics of the shorted anode lateral insulated gate bipolar transistor (SA-LIGBT) is explained through two-dimensional numerical simulation. The NDR regime is an inherent feature of all SA-LIGBTs, and results from the two different conduction mechanisms responsible for current flow in the device. These conduction mechanisms are minority-carrier injection and majority-carrier flow. Since both the anode geometry and the doping profile control the onset and the degree of minority-carrier injection, the effect these parameters have on the NDR is investigated. A simple lumped-element equivalent model of the SA-LIGBT allows qualitative predictions to be made on how changes in the device geometry and doping profiles influence the NDR regime. It is shown that conductivity modulation is a necessary but not sufficient condition for the occurrence of negative resistance in SA-LIGBT devices. Also required is a large voltage drop in the high-resistivity drift region before conductivity modulation is initiated. This causes small changes in the anode current level, greatly decreasing the total resistance across the drift region     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

AlGaN/GaN HEMT器件工艺的研究进展

首先论述了Al GaN/GaN高电子迁移率晶体管(HEMT)在微波大功率领域的应用优势和潜力;其次,介绍并分析了影响Al GaN/GaN HEMT性能的主要参数,分析表明要提高Al-GaN/GaN HEMT的频率和功率性能,需改善寄生电阻、电容、栅长和击穿电压等参数。然后,着重从材料结构和器件工艺的角度阐述了近年来Al GaN/GaN HEMT的研究进展,详细归纳了目前主要的材料生长和器件制作工艺,可以看出基本的工艺思路是尽量提高材料二维电子气的浓度和材料对二维电子气的限制能力的同时减小器件的寄生电容和电阻,增强栅极对沟道的控制能力。另外,根据具体情况调节栅长及沟道电场。最后,简要探讨了Al GaN/GaN HEMT还存在的问题以及面临的挑战。     

DC and microwave characteristics of sub-0.1-μm gate-lengthplanar-doped pseudomorphic HEMTs

Analytical modeling of these very-short-channel HEMTs (high-electron-mobility transistors) using the charge-control model is given. The calculations performed using this model indicate a very high electron velocity in the device channel (3.2±0.2×10⁷ cm/s) and clearly demonstrate the advantages of the planar-doped devices as compared to the conventional uniformly doped HEMTs. Devices with different air-bridged geometries have been fabricated to study the effect of the gate resistance on the sub-0.1-μm HEMT performance. With reduced gate resistance in the air-bridge-drain device, noise figures as low as 0.7 and 1.9 dB were measured at 18 and 60 GHz, respectively. Maximum available gains as high as 13.0 dB at 60 GHz and 9.2 dB at 92 GHz, corresponding to an f_max of 270 GHz, have also been measured in the device. Using the planar-doped pseudomorphic structure with a high gate aspect-ratio design, a noise figure of less than 2.0 dB at 94 GHz is projected based on expected further reduction in the parasitic gate and source resistances     

Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs

The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail. By careful design, the short channel short channel effects can be suppressed by the elevated source/drain (S/D) structure. In addition, the S/D region parasitic capacitance is significantly suppressed by the silicon-on-insulator (SOI)-like S/D structure. Tradeoff between series resistance and gate-to-drain Miller capacitance can be achieved by carefully selecting the gate spacer thickness. With careful optimization of device geometry, both the gate-delay and power consumption can be significantly reduced together. Design guideline and potential performance gain with the S/D-on-insulator structure is discussed.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Experimental study of hot-carrier effects in LDMOS transistors

Hot-carrier currents and the induced degradation mechanisms in lateral double-diffused MOS (LDMOS) transistors for smart power applications are investigated in detail. Three different regions within the device where significant hot-carrier generation can occur depending on bias as well as device technological parameters have been identified. Guidelines to suppress the degradation mechanisms involving the two lightly doped regions of the device not overlapped by the gate electrode, responsible for the stronger device degradation, are provided. Devices optimized according to the given guidelines have been fabricated and demonstrate a strong hot carrier resistance