p+多晶Si1-xGex功函数对异质结CMOS器件电学特性影响的模拟研究

为使垂直层叠SiGe/Si异质结CMOS器件具有匹配的阈值电压,利用二维器件模拟器MEDICI模拟分析了p 多晶Si1-xGex栅的功函数对此类器件直流与交流特性参数的影响,得出在P 多晶Si1-xGex功函数W=0.85 eV,即Ge组分x=0.36时,此类器件的p-MOSFET与n-MOSFET具有匹配的阈值电压,分别为VTp=-0.215 V和VTn=O.205 V.为此类器件的优化设计和制备提供了理论依据.     

Si1-xGex/Si应变材料的生长及热稳定性研究

利用分子束外延（MBE）技术生长了Ge组份为0.1-0.46的Si1-xGex外延层。X射线衍射线测试表明，SiGe/Si异质结材料具有良好的结晶质量和陡峭界面，其它参数与可准确控制。通过X射线双晶衍射摆曲线方法，研究了经700℃、800℃和900℃退火后应变SiGe/Si异质结材料的热稳定性。结果表明，随着退火温度的提高，应变层垂直应变逐渐减小，并发生了应变弛豫，导致晶体质量退化；且Ge组分越小，Si1-xGex应变结构的热稳定性越好；室温下长时间存放的应变材料性能稳定。     

应变Si/(001)Si_(1-x)Ge_x能带结构模型

应变Si材料的能带结构是研究设计高速/高性能器件和电路的理论基础。采用结合形变势理论的K.P微扰法建立了(001)面弛豫Si1-xGex衬底上生长的张应变Si的能带结构模型。结果表明:[001]、[001]方向能谷构成了张应变Si导带带边,其能量值随Ge组分的增加而变小;导带劈裂能与Ge组分成线性关系;价带三个带边能级都随Ge组分的增加而增加,而且Ge组分越高价带带边劈裂能值越大;禁带宽度随着Ge组分的增加而变小。该模型可获得量化的数据,对器件研究设计可提供有价值的参考。     

应变Si/(111)Si1-xGex带边能级计算

采用结合形变势理论的k.p微扰法计算了（111）面弛豫Si1-xGex衬底生长双轴应变Si材料的带边能级。结果表明,应变Si/(111)Si1-xGex材料导带简并度与弛豫Si材料相同,价带带边简并度在应力的作用下部分消除,导带和价带带边能级均随着Ge组份（x）的增加而增加。此外,本文还给出了禁带宽度、价带劈裂能随Ge组份（x）的函数关系。以上量化结论可为Si基应变器件设计提供有价值的参考。     

应变Si/(001)Si_(1-x)Ge_x价带结构

应变SiCMOS技术是当前国内外研究发展的重点,在高速/高性能器件和电路中有极大的应用前景。基于(001)面弛豫Si1-xGex衬底上生长的张应变Si的价带E(k)-k关系模型,研究获得了[100]和[001]晶向的价带结构及相应的空穴有效质量。结果表明,与弛豫材料相比,应变引起了应变Si/(001)Si1-xGex价带顶的劈裂,且同一晶向族内沿[001]和[100]两个晶向的价带结构在应力的作用下不再对称,相应的空穴有效质量随Ge组份有规律地变化。价带空穴有效质量与迁移率密切相关,该结论为Si基应变PMOS器件性能增强的研究及导电沟道的应力与晶向设计提供了重要理论依据。     

(101)面生长双轴应变Si带边模型

采用结合形变势理论的k·p微扰法建立了(101)面弛豫Si1-xGex衬底上生长的双轴应变Si的带边模型. 结果表明：［001］, ［001］,［100］及［100］方向能谷构成了该应变Si的导带带边,其能量值随Ge组分的增加而增加;导带劈裂能与Ge组分成正比例线性关系;价带三个带边能级都随Ge组分的增加而增加,而且Ge组分越高价带带边劈裂能值越大;禁带宽度随着Ge组分的增加而变小. 该模型可获得量化的数据,为器件研究设计提供有价值的参考.     

(101)面生长双轴应变Si带边模型

采用结合形变势理论的k·p微扰法建立了(101)面弛豫Si1-xGex衬底上生长的双轴应变Si的带边模型.结果表明:[001],[001],[100]及[100]方向能谷构成了该应变Si的导带带边,其能量值随Ge组分的增加而增加;导带劈裂能与Ge组分成正比例线性关系;价带三个带边能级都随Ge组分的增加而增加,而且Ge组分越高价带带边劈裂能值越大;禁带宽度随着Ge组分的增加而变小.该模型可获得量化的数据,为器件研究设计提供有价值的参考.     

深亚微米应变SiGe沟PMOSFET特性模拟

为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力     

太赫兹Si/SiGe量子级联激光器的能带设计

使用nextnano3模拟软件计算Si/Si1-xGex/Si量子阱的能带结构,对Si/SiGe量子级联激光器有源区的能带结构进行设计,结果表明使用Ge组分为0.27～0.3,量子阱宽度为3nm的SiGe合金与垒宽为3nm的Si层构成对称应变级联异质结构,有利于优化THz Si/SiGe量子级联激光器结构.     

太赫兹Si/SiGe量子级联激光器的能带设计

使用nextnano3模拟软件计算Si/Si1-xGex/Si量子阱的能带结构,对Si/SiGe量子级联激光器有源区的能带结构进行设计,结果表明使用Ge组分为0.27～0.3,量子阱宽度为3nm的SiGe合金与垒宽为3nm的Si层构成对称应变级联异质结构,有利于优化THz Si/SiGe量子级联激光器结构.     

激光辐照硅、锗材料形成表面波纹的实验研究

用光学显微镜分别测量了1．06μm激光辐照硅、锗材料形成表面波纹的形貌特征。在激光辐照材料形成初始表面波纹之后，后继激光对最终波纹的增长起正反馈作用。当激光功率密度略大于材料损伤阈值时，材料表面呈现周期性的波纹结构；当激光功率密度远大于材料损伤阈值时，材料熔融区内出现无规则的随机分布波纹。激光辐照硅、锗材料产生的波纹结构与材料的性能、表面状况和实验中使用的激光参数密切相关。同时，分析了表面波纹结构对激光光束传输特性，以及激光与材料相互作用产生破坏效应的影响。     

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.     

Strained-$hbox{Si}_{1 - x}hbox{Ge}_{x}/hbox{Si}$ Band-to-Band Tunneling Transistors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switching Behavior

Strained pseudomorphic Si/Si_1-xGe_x/Si gate-controlled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration in the 10¹⁹-10²⁰ cm^-3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are compared to simulations using a nonlocal BTBT model to analyze the mechanisms of device operation and to understand the impact of these parameters on the device switching behavior. The measured characteristics are consistent with simulation analysis that shows a reduction in energy barrier for tunneling (E_geff) and a reduction in tunneling distance with increasing Ge composition and source doping concentration. Increases in the pseudomorphic layer Ge content and doping concentration of the tunnel junction produce large improvements in the measured switching-behavior characteristics (I_on, slope, turn-on voltages, and sharpness of turn-on as a function of V_ds). Simulations are also performed to project the potential performance of more optimized structures that may be suitable for extremely low power applications (V_dd < 0.4 V).     

1.55μmSi_(1-x)Ge_x/Si光开关与光探测器集成的分析及设计

对１．５５μｍ波长的Ｓｉ１－ｘＧｅｘ光波导开关和Ｓｉ１－ｘＧｅｘ／Ｓｉ红外探测器的集成结构进行了系统的理论分析和优化设计。设计结果为：（１）对Ｓｉ１－ｘＧｅｘ光开关，Ｇｅ含量ｘ＝０．０５，波导的内脊高、脊宽和腐蚀深度分别为３，８．５和２．６μｍ，分支角为５～６°。要实现对１．５５μｍ波长光的开关作用，ｐｎ＋结上所需加的正向偏压值应为０．９７Ｖ；（２）对Ｓｉ１－ｘＧｅｘ／Ｓｉ探测器，Ｇｅ含量ｘ＝０．５，探测器由２３个周期的６ｎｍＳｉ０．５Ｇｅ０．５和１７ｎｍＳｉ交替组成厚度为５５０ｎｍ，长度约为１．５～２ｍｍ的超晶格，内量子效率达８０％以上。     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

近红外Si_(0.8)Ge_(0.2)/Si横向pin探测器的模拟与测试

设计了一种新型叉指状近红外 Si0 .8Ge0 .2 / Si pin横向光电探测器。采用半导体器件模拟软件 Atlas分别对该器件平衡条件下物理特性及反向偏压下电场分布、光电特性进行了模拟 ;对实际制作的光电探测器进行了测试 ,结果表明 :其波长响应范围为 0 .4～ 1 .3μm,峰值响应波长在 0 .93μm,响应度达 0 .3 8A/ W,寄生电容小于 2 .0 p F。实验结果和模拟结果符合得很好。其良好的光电性能为应用于近红外光的高速、低工作电压硅基光电集成器件提供了可能     

Effect of Si capping layer on the interface quality and NBTI of high mobility channel Ge-on-Si pMOSFETs

The effects of a Si capping layer on the device characteristics and negative bias temperature instability (NBTI) reliability were investigated for Ge-on-Si pMOSFETs. A Ge pMOSFET with a Si cap shows a lower subthreshold slope (SS), higher transconductance (G_m) and enhanced drive current. In addition, lower threshold voltage shift and G_m,max degradation are observed during NBTI stress. The primary reason for these characteristics is attributed to the improved interface quality at the high-k dielectric/substrate interface. Charge pumping was used to verify the presence of lower density of states in Ge pMOSFETs with a Si cap.     

Si和SiGe三极管Early效应模型及在电路仿真器中的应用综述

Early效应作为表征双极器件关键性能的因素之一,影响输出跨导、传输电流、基区渡越时间、电流增益、扩散电容等器件特性。本文从Early效应的基本定义出发,综述了Early电压的起源,模型的发展及其在Si和SiGe电路仿真器中的应用。具体为：（1）综述了Si三极管中的基本模型及在SPICE中处理过程,然后针对SPICE的缺陷,描述了VBIC模型中针对Early效应的改进。（2）由于SPICE和VBIC不能有效描述SiGe HBT中基区Ge组分引入。本文基于SiGe HBT标准化模型Mextram、HICUM对SiGe HBT的建模思想,综述了将其用于建立Early电压模型的方法。（3）总结了现有主流模型对Early效应的建模方法及优缺点。     

Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟,给出了以提高跨导为目标的Si/SiGe PMOSFET优化设计方法,包括栅材料的选择、沟道层中Ge组分及其分布曲线的确定、栅氧化层及Si盖帽层厚度的优化和阈值电压的调节,基于此已研制出Si/SiGe PMOSFET器件样品.测试结果表明,当沟道长度为2μm时,Si/SiGe PMOS器件的跨导为45mS/mm(300K)和92mS/mm(77K),而相同结构的全硅器件跨导则为33mS/mm(300K)和39mS/mm(77K).     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.