SCR 器件在深亚微米CMOS静电保护电路中的应用

:CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制.因此,对ESD保护的要求也更加严格,需要采取更加有效而且可靠的ESD保护措施.针对近年来SCR器件更加广泛地被采用到CMOS静电保护电路中的情况,总结了SCR保护电路发展过程中各种电路的工作机理.旨在为集成电路设计人员提供ESD保护方面的设计思路以及努力方向.     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

毫米波CMOS集成电路的现状与趋势

随着深亚微米和纳米CMOS工艺的成熟,设计和实现低成本的毫米波CMOS集成电路已成为可能.简述了毫米波CMOS技术的发展现状,介绍了毫米波CMOS集成电路的关键技术,即晶体管建模和传输线建模,并给出了毫米波CMOS电路的最新进展和发展趋势.     

一种改进的片内ESD保护电路仿真设计方法

对现有的片内ESD保护电路仿真设计方法进行了改进,使之适用于深亚微米工艺.文中设计了新的激励电路以简化仿真电路模型;增加了栅氧化层击穿这一失效判据;使用能量平衡方程描述深亚微米MOSFET的非本地输运,并对碰撞离化模型进行了修正;使用蒙特卡罗仿真得到新的电子能量驰豫时间随电子能量变化的经验模型.最后使用文中改进的仿真设计方法对一个ESD保护电路进行了设计和验证,测试结果符合设计要求.     

深亚微米集成电路的快速时域仿真技术

随着深亚微米集成电路技术的发展，集成电路的规模越来越大，工作频率越来越高，并正朝着系统集成的方向发展，因而在模拟速度，模拟精度和可模拟的电路规模等各个方面对电路仿真技术提出了新的要求。近年来，各种新的电路仿真方法和仿真系统用相继脱颖百出，并将取代那些传统的，已经无法适应深亚微米技术发展的电路仿真器。     

业界要闻

我国深亚微米集成电路设计技术获重大突破 由上海交通大学大规模集成电路研究所研制成功的“深亚微米集成电路设计技术”,日前通过教育部专家鉴定。 上海交大在“深亚微米集成电路设计技术”研究中所包含的器件建模、延时网络、参数提取、数据库及管理、逻辑综合、电路模拟、版图没计、物理验证等设计技术总体水平达到国际先进水平。其中在0.25μm级深亚微米芯片设计技术中的“逻辑综合与物理设计一体化理论”,属国际首创。交大今后将与国内有关企业加强合作,尽快实现我国深亚微米集成电路设计技术及芯片的产业化。     

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.     

基于CMOS工艺的射频集成电路ESD保护研究

随着工艺特征尺寸的缩小,射频集成电路承受的静电放电(ESD)问题日趋变得复杂.保护电路与被保护核心电路的相互影响,已经成为制约射频集成电路发展的一个障碍.本文主要研究CMOS工艺下,ESD保护电路与被保护核心电路之间的相互影响的作用机理,提出研究思路,并对射频集成电路ESD保护电路的通用器件作出评价.1.引言随着半导体...     

深亚微米集成电路制造工艺设计与仿真系统TSUPREM发展与现状

结合集成电路制造工艺仿真系统TSUPREM的发展历史，回顾了集成电路工艺仿真技术的发展，并着重介绍了Avanti公司的深亚微米工艺仿真系统TSUPREM-4 1999.4。     

RF 集成电路工艺探讨¹

射频集成电路的研究和制作将大大拓展集成电路的应用空间，本文介绍了当今RF的主流工艺，并分别对基于硅的深亚微米CMOS工艺在RF设计中的可行性和困难进行了研究，评述了其中存在的问题，最后提出了该领域中未来的发展前景。     

ESD应力下n阱扩散电阻的潜在损伤

电阻在静电放电(Electrostatic Discharge,ESD)保护电路中,起隔离和分压的作用。利用传输线脉冲(Transmission Line Pulsing,TLP)测试系统,在宽度为100ns的脉冲作用下,研究了n阱扩散电阻在ESD应力下的工作特性。结果表明,n阱扩散电阻在发生初次瞬态击穿(瞬态击穿电压79.0V,瞬态击穿电流1.97A)后,由于阳极n+-n结构被破坏,内部结构已经出现潜在损伤,不再具备隔离和分压的作用。     

Process influence on product CDM ESD performance

Effective ESD protection circuit design has become challenging due to rapid advances in process technology. This study was launched to address those concerns in deep sub-micron technologies and to look for a process windows that preserve CDM ESD robustness for a given ESD protection designs. Experimental results for 0.18 μm integrated CPU’s together with process window effects on CDM robustness are presented and discussed. The correlation between electrical characteristics and some of the common failure modes are described. It is shown that transistor off current lower than critical value can lead to degradation in time and an eventual secondary breakdown in a parasitic NPN transistor that results in unexpected CDM sensitivity.     

Body ballast resistor enhances ESD robustness of deep sub-micron CMOS circuit

In this paper, the body ballast resistor design is introduced in electrostatic discharges (ESD) protection circuit for deep submicron CMOS integration circuit applications. With having the resistor, the ESD strength, turn-on resistance and trigge-on speed are greatly modulated. Those good characteristics enhance the efficiency of ESD protection circuit and keep the gate-oxide away from ESD damages. The consequence is caused from the fact that body ballast resistor builds up a positive substrate potential during the ESD stressing; consequently, reduces source to substrate barrier height. It should be further addressed that only a few design complexity is added, which is especially useful in deep sub-micron ULSI manufacturing.     

A case study of defects due to process marginalities in deep sub-micron technology

The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in and below deep sub-micron technology node. Most of the defects causing chip leakage are detectable with only one of the failure analysis (FA) tools such as liquid crystal detection (LCD) or photon emission microscope (PEM). However, due to process marginalities some defects are often not detectable with only one FA tool [Hung-Sung Lin, Wen-Tung Chang, Chun-Lin Chen, Tsui-Hua Huang, Vivian Chiang, Chun-Ming Chen. A study of asymmetrical behaviour in advanced nano SRAM devices. In: 13th IPFA proceedings; July 2006. p. 63–6; Kruseman Bram, Majhi Ananta, Hora Camelia, Eichenberger Stefan, Meirlevede Johan. Systematic defects in deep sub-micron technologies. ITC international test conference, 2004. p. 290–9.]. This paper present an example of an abnormal power consumption process related defect which could only be detected with more advanced FA tools.     

SOC基于LFSR的混合模式测试

随着集成电路深亚微米制造技术和设计技术迅速发展,系统芯片(SOC)作为一种解决方案得到了越来越广泛的应用。SOC的测试中,内建自测试(Built.In Self-Test,BIST)成为人们研究的热点。文中对SOC的设计特点及其BIST中的混合模式测试进行了探讨。     

VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.     

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 10⁷ gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.     

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.