Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.     

Application of anodization in Oxygen plasma to fabrication of GaAs IGFET's

Anodic oxide grown in oxygen plasma has been used to fabricate the gate insulator of GaAs insulated-gate field-effect transistors (IGFET's), by patterning the gate electrode of 1.2 µm in length with the dry etching process. It is found that the oxidation process does not damage the electrical property of the channel layer. However, the trap states at the interface between the oxide and the channel affect the low-frequency characteristics, especially at positive gate voltage. The IGFET's show a good high-frequency performance comparable to GaAs MESFET's. The following characteristics are confirmed from the measurement of the S-parameters and the equivalent circuit analysis; the maximum stable power gain is 11.4 dB at 8 GHz, the cut-off frequency of the unilateral power gain is 48 GHz, and the intrinsic gain-bandwidth product is 18 GHz. The minimum noise figure is measured to be 4.8 dB at 8 GHz.     

A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs

The role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O₂ based high density plasma was studied. HBr/O₂-based polysilicon etch process used in this study seems to be highly selective to the underlying oxide and produce a dielectric fill-friendly post-etch profile depending on the flow rates of HBr and oxygen. When appropriate amounts of HBr and oxygen (∼30 sccm of HBr and ∼3 sccm of oxygen) are present in the etch plasma, brominated silicon oxide seems to be deposited on the original gate oxide and the gate stack sidewall from the reaction of SiBr_x (reaction product during polysilicon etch step) and oxygen during the HBr/O₂-based oxide etch process. The deposited brominated oxide on the thin gate oxide seems to make the HBr/O₂-based plasma etch process extremely selective to the thin gate oxide by protecting the underlying gate oxide. The deposited brominated oxide on the gate stack sidewall seems to prevent the notching by protecting the sidewall during gate stack etching. The etch rate of the brominated oxide seems to be much faster than that of the thermal oxide during the 200:1 diluted HF cleaning. However, the deposited brominated oxide on the thin gate oxide and the gate stack sidewall during the plasma etching survived the following 1 min 200:1 diluted HF cleaning, as was observed in a TEM micrograph (Fig. 2(a)).     

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.     

一种新的等离子体边缘损伤的测量方法

在等离子体刻蚀多晶硅工艺中 ,栅边缘氧化层直接暴露在等离子体环境中 ,由于 U V射线的作用栅边缘处将会产生损伤 ,这种损伤包含了大量的界面态和氧化层陷阱 .文中讨论了等离子体边缘损伤与圆片位置关系、天线比之间的关系及它们对器件长期可靠性的影响 ,并使用了低频局部电荷泵技术 .测量的结果包含了损伤产生的快、慢界面态和氧化层陷阱的信息 ,可以较好地测量工艺中产生的栅边缘损伤 ,为评估薄栅 MOSFET的栅边缘损伤提供了一种简单快捷的方法     

深亚微米CMOS布线工艺中等离子对薄栅氧损伤的预防研究

A comparison is made of several plasma-induced damage(PID) measurement techniques.A novel PID mechanism using high-density plasma(HDP) inter-metal dielectric(IMD) deposition is proposed.The results of a design of experiment(DOE) on Ar pre-clean minimizing PID are presented.For HDP oxide deposition,the plasma damage is minimal,assuring minimal exposure time of the metal line to the plasma using a maximal deposition to sputter ratio.This process induces less PID than classic SOG processing.Ar pre-clean induces minimal plasma damage using minimal process time,high ion energy and high plasma power.For metal etching,an HDP etch is compared to a reactive ion etch,and the impact of the individual process steps are identified by specialized antenna structures.The measurement results of charge pumping,breakdown voltage and gate oxide leakage correlate very well.On metal etching,the reactive ion etching induces less plasma damage than HDP etching.For both reactors, PID is induced only in the metal over-etch step.     

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis

This paper presents oxide trap characterization of nitrided and non-nitrided gate oxide N-MOSFETs using low frequency noise (LFN) measurements. The identification of defects generated by the gate oxide growth and the nitridation process is carried out using random telegraph signal noise analysis. Significant properties of traps induced by the nitridation process are pointed out. Main trap parameters, such as their nature, capture and emission times, cross-sections, energy levels, and position with respect to the Si/SiO₂ interface, are extracted. These results illustrate the potential of noise investigation for oxide characterizations.     

Evaluation technique of gate oxide damage

Gate oxide damage by plasma processing was evaluated using structures with various antenna lengths. The gate oxide damage by plasma processing was found to be monitored quantitatively by measuring the charge to breakdown, Q_BD. From the Q_BD measurements, we have confirmed that the degradation occurs during overetching, not in main etching. Plasma current was calculated from the decrease of Q_BD during the etching. The breakdown spot in the gate oxide was detected by photon emission and TEM. The LOCOS structure plays an important role for the degradation by plasma damage. In this paper, it is demonstrated that the Q_BD method is effective for realizing a highly reliable process against plasma damage     

Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements

We have investigated gate and drain current noise on strained-channel n-MOSFETs with a SiGe virtual substrate and a 12 Å thermally nitrided gate oxide using low frequency noise measurements. The power spectral densities (PSD) of the flat-band voltage fluctuations are extracted from both gate and drain current noise. We show that the same oxide trap density profile is involved in drain and gate low frequency noise. A comparison with standard n-MOSFET transistors with the same gate stack process is presented. The flat-band voltage PSD concept is also used to compare both technologies to show that bulk and dielectric quality of strained devices are not degraded with regard to standard n-MOSFETs.     

双栅氧LDMOS器件工艺技术的研究与改进

双栅氧LDMOS器件刻蚀过程中极易造成多晶硅残留现象,降低了栅极和源区之间的击穿电压.改进了制备双栅氧LDMOS器件的方法,对于70 nm以下的栅氧厚度,采用保留整个厚栅氧器件区域栅氧的刻蚀方法,同时用一次多晶工艺代替二次多晶工艺,消除了多晶硅残留现象,减少了工艺步骤,提高了成品率;对于厚度大于70 nm或者100 nm的厚栅氧器件,除了以上的改进措施,还增加了一步光刻工艺,分别单独形成高压和低压器件的源漏区域.通过这些方法,解决了多晶残留问题,得到了性能更好的LDMOS器件,大大提高了成品率.     

Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

We study failure mechanisms in 0.35μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices stressed by high current - ESD like - pulses. Stress evolution of leakage current and low frequency noise is correlated with the position of the ESD damage analyzed using optical beam induced current (OB1C) technique. While a kink-free-like IV characteristics and low noise magnitude are typical for a bulk damage at the drain-contact region, a kink-like IV shape and large random telegraph signal (RTS) noise accompanies surface damage under the gate oxide. The role of hot-carriers in the degradation of the Si/Si0₂ interface and gate oxide, and leakage current mechanism are discussed.     

Effects of plasma charging damage on the noise performance ofthin-oxide MOSFET's

The effects of plasma charging damage on the noise properties of MOSFET's which is a necessary consideration for high-performance analog applications were studied using 1/f noise, Random Telegraph Signal (RTS) noise and charge pumping techniques. Plasma ashing significantly increases the drain flicker noise, more with larger antenna sizes, mainly in the low-frequency and low-gate-bias regime. The observed RTS reveals that an oxide trap with a few milliseconds time constant was induced by the plasma processing. This oxide trap is located in the energy space which corresponds to the low gate bias of device. This trap may be reproduced by Fowler Nordheim stress as suggested by noise and charge pumping measurements, supporting the notion that plasma ashing damage is a result of electrical stress, not radiation, for example     

Effect of plasma poly etch on effective channel length and hotcarrier reliability in submicron transistors

The effective channel length (L_eff)) variation resulting from exposure to the plasma during the poly-etch step was investigated. The plasma induced charging effect was also studied using gate polysilicon antenna structures. It was found that, due to the poly etching, the L_eff variation has a larger impact on the fully processed transistor transconductance characteristics than the charging effect in the gate oxide region. It is believed that the damage in the LDD region, which gives rise to the L_eff variation, imposes a serious hot carrier reliability problem     

The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors     

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance