有源层厚度对氧化铟镓锌薄膜晶体管性能的影响

使用磁控溅射法制备了IGZO-TFT,研究有源层厚度对其电学性能的影响。实验结果表明,器件的阈值电压和开关比会随着有源层厚度的增大而减小,而器件的亚阈值摆幅和饱和迁移率则会随有源层厚度的增大而增大。此外,还研究了有源层厚度对器件偏压稳定性的影响。有源层厚度越大的器件,其阈值电压漂移也会越大。这主要与半导体层中所增加的缺陷态密度有关。     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

水基溶液法IGZO-TFT的电学特性研究

采用水基溶液法制备铟镓锌氧化物薄膜晶体管(IGZO-TFT),研究了在有无紫外光辅助退火条件下,不同后退火温度(270,300,330,360和400℃)对IGZO-TFT器件电学性能的影响。研究发现,IGZO-TFT在后退火温度为360℃时器件电学性能最佳,从而证明了水基溶液法在小于400℃的低温下可以制备IGZO-TFT。同时,研究表明,在后退火温度为360℃时,与无紫外光辅助退火IGZO-TFT相比,经紫外光辅助退火IGZO-TFT的饱和迁移率从1.19cm^(2)/Vs增加到1.62cm^(2)/Vs,正栅偏压偏移量从8.7 V降低至4.6 V,负栅偏压偏移量从-9.7 V降低至-4.4 V,从而证明了紫外光辅助退火对IGZO薄膜具有激活与钝化作用,可以优化IGZO-TFT器件的电学性能。     

氧分压对射频溅射制备ZTO沟道层的薄膜晶体管器件性能的影响

以锌锡氧化物(ZTO)薄膜作为沟道层,聚甲基丙烯酸甲酯(PMMA)薄膜作为介质层低温(100℃)制备了顶栅共面结构的薄膜晶体管(TFT),并研究了ZTO沟道层成膜过程中氧分压对器件性能的影响。结果表明,ZTO沟道层具有稳定的非晶结构、较高的可见光透明性(在400~700nm范围内平均透过率大于等于89.61%),且增大氧分压有利于其可见光透明性的提升。霍尔测试结果表明,增大氧分压(由3.5×10-2Pa增大到7.5×10-2Pa)会降低ZTO电子载流子浓度(由4.73×10¹⁵cm-3降低到6.11×10¹²cm-3),致使基于ZTO沟道层TFT器件的能耗降低(表现为关态电流的降低和耗尽型器件阈值电压的正向移动)。此外,增大氧分压还有益于沟道层/介质层界面状态的优化,即亚阈值摆幅减小。     

等离子体处理对非晶IGZO柔性薄膜晶体管性能的影响

本文研究了柔性基板上的薄膜晶体管,使用IGZO作为有源层,栅极绝缘层采用NH3等离子体和N2O等离子体分别进行处理,研究器件性能变化。结果表明等离子体类型及处理时间对阈值电压、场效应迁移率、开关比、亚阈值摆幅（SS）和偏压稳定性都有影响。TFT器件用NH3等离子体处理10秒显示出最佳的器件性能,阈值电压达到0.34 V,场效应迁移率为15.97 cm2/Vs,开关比为6.33×107,亚阈值摆幅为0.36 V /dec。本文提出的柔性IGZO-TFT是下一代柔性显示驱动装置较好选择。     

直流和交流溅射沟道材料对铟镓锌氧薄膜晶体管性能的影响

研究了在TFT制备过程中,直流溅射和交流溅射生长铟镓锌氧薄膜对器件的转移特性和栅偏压应力特性的影响。交流溅射生长的IGZO制备的器件具有较低的阈值电压和较好的亚阈特性,分别为0.937 V和0.34 V/dec;而直流溅射得到的阈值电压和亚阈值摆幅则分别是:1.78V和0.50 V/dec。对于稳定性,在30 V的栅极应力下,直流溅射得到的器件的阈值电压漂移则相对小一些。本文通过分析直流和交流溅射的过程中薄膜的沉积情况,阐述了上述现象产生的原因。     

CuPc有机薄膜晶体管稳定性研究

以酞菁铜为有源层,二氧化硅为绝缘层,钛/金作为电极,制作了沟道宽长比为6 000/10的有机薄膜晶体管。通过比较在不同时期器件在空气环境中的电学特性,分析了环境对器件电学性能的影响。结果表明,在其他条件不变的情况下,当器件置于空气中时,其载流子的浓度和体电导率逐渐增大,迁移率几乎不受影响;相同栅极电压下器件达到饱和状态所需的源漏电压增大,线性区向饱和区推进;阈值电压减小,在栅极电压为0时,界面处逐渐形成导电沟道,器件从增强型向耗尽型转变。     

氧等离子气氛中NMOS器件的性能退化

文章描述了氧等离子干法剥离光刻胶中MOS器件的性能退化问题,并且制备了不同天线比AR(Antenna Ratio),相同器件结构的NMOS器件来检测器件的退化.实验结果发现栅漏电流密度Jg和阈值电压Vt漂移会随着Al的天线面积的增加而非线性地增加,尤其表现在阈值电压漂移上.运用增加电流应力时间的测试来模拟器件在等离子反应腔中所受的实际应力,发现了与天线比增加时阈值电压变化趋势相同,表明在氧等离子气氛中器件受到了负电应力的影响.最后,基于此次实验的结果,在器件的设计,工艺参数的制定方面提出了一些减小干法剥离光刻胶工艺带来器件性能退化的建议.     

总剂量加固对SOINMOS器件抗辐射特性的影响

采用埋层改性工艺对部分耗尽SOI NMOS器件进行总剂量加固,通过测试器件在辐射前后的电学性能研究加固对SOI NMOS器件抗辐射特性的影响。加固在埋氧层中引入电子陷阱,辐射前在正负背栅压扫描时,电子陷阱可以释放和俘获电子,导致背栅阈值电压产生漂移,漂移大小与引入电子陷阱的量有关。通过加固可以有效提高器件的抗总剂量辐射特性,电子陷阱的量对器件的抗辐射性能具有显著影响。     

基于喷墨打印的In2 O3/IGZO TFT的电学性能

利用喷墨打印技术制备了非晶铟镓锌氧化物(IGZO)薄膜、铟氧化物(In_2O_3)薄膜和性能明显改善的双层In_2O_3/IGZO异质结沟道薄膜,研究了薄膜的物理与电学特性。结果表明,喷墨打印制备的金属氧化物薄膜具有较高的光学透过率与较低的表面粗糙度;嵌入的In_2O_3层薄膜能减小IGZO与In_2O_3间的界面缺陷,明显提高In_2O_3/IGZO薄膜晶体管(TFT)的性能及其偏压稳定性。随着IGZO中In含量的增加,载流子浓度升高,器件的迁移率增大,但In_2O_3与IGZO间能级势垒会逐渐降低,最后导致难以控制关态电流和阈值电压,因此,适当调整In的比例有利于获得较高器件性能的In_2O_3/IGZO异质结沟道TFT。     

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.     

Influence of channel layer and passivation layer on the stability of amorphous InGaZnO thin film transistors

The electrical stability of amorphous InGaZnO (a-IGZO) TFTs with three different channel layers was investigated. Compared with the single channel layer, the a-IGZO TFT with double stacked channel layer showed the lowest threshold voltage shift with slightly change in field effect mobility and sub-threshold swing under positive and negative gate bias stress tests. Moreover, sputtered SiN_x thin film was served as passivation layer where the V_th shift in bias stress effect evidently became less. It was found that the passivated a-IGZO TFT with double stacked channel layer still exhibited the best stability. The results prove that the stability of a-IGZO TFTs can be effectively improved by using double stacked channel layer and passivation layer.     

Channel Protection Layer Effect on the Performance of Oxide TFTs

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al‐doped zinc tin oxide (AZTO) TFT. Deposition of an ultra‐thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo‐resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.     

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive V_TH shift within 0.4 V and negative V_TH shift within-1.2 V and it is robust and promising for high-resolution display.     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Improved reliability of large-sized a-Si thin-film-transistor by back channel treatment in H2

A hydrogen plasma treatment on the back-channel region of large-sized amorphous silicon thin film transistor (a-Si TFT) with high RF power and optimal process time of 20 s is proposed in this work to effectively reduce off current (I_off) and threshold voltage (V_th) shift under high and low electrical-field stresses. The channel width (W) of large-sized a-Si TFT is ranged from 1000 to 10,000 μm, which are comparable to the realistic TFTs used in the gate driver on array (GOA) of display. It is experimentally found that the mechanism of V_th shift (ΔV_th) after high electrical stress is dominated by the defect generation in a-Si layer rather than charge trapping in the gate insulator (GI) layer, which is different from the observation in previous literatures. It could be due to the effects of back-channel treatment (BCT). In addition, after low electrical stresses, the mechanism of ΔV_th is dominated by defect generation in a-Si layer, which is consistent with previous reports.     

Electrical stability of pentacene thin film transistors

The influence of environmental conditions on the device operation and the stability of polycrystalline pentacene thin film transistors (TFTs) were investigated. Electrical in-situ and ex-situ measurements of staggered pentacene TFTs were carried out to study the influence of dry oxygen and moisture on the device stability. The transistors were fabricated by organic molecular beam deposition on thermal oxide dielectrics. Oxygen exposure of the pentacene films lead to the creation of acceptor-like states in the bandgap. The acceptor-like states cause a shift of the onset of the drain current towards positive gate voltages. The charge carrier mobility and the on/off ratio of the transistor are not affected by the acceptor-like states. Furthermore, the acceptor-like states have an influence on the stability of the TFTs. Devices exposed to oxygen exhibit a shift of the threshold voltage upon prolonged biasing. Transistors characterized under vacuum conditions (no oxygen exposure) do not exhibit a shift of the threshold voltage (bias stress effect) as a consequence of prolonged biasing. The experimental results show a clear correlation between the device behavior upon oxygen exposure and the stability of the devices. The shift of the onset voltage upon oxygen exposure correlates with the shift of the threshold voltage upon prolonged bias. The influence of dry oxygen on the onset voltage, the threshold voltage, and the electrical stability will be described. Furthermore, the influence of bias stress on the operation of organic circuits like an active matrix addressed OLED displays will be discussed.     

A high-endurance low-temperature polysilicon thin-film transistorEEPROM cell

A planar type polysilicon thin-film transistor (poly-Si TFT) EEPROM cell with electron cyclotron resonance (ECR) N₂O-plasma oxide has been developed with a low temperature (⩽400°C) process. The poly-Si TFT EEPROM cell has an initial threshold voltage shift of 4 V for programming and erasing voltages of 11 V and -11 V, respectively. Furthermore, the poly-Si TFT EEPROM cell maintains the threshold voltage shift of 4 V after 100 000 program/erase cycles. The excellent high endurance of the fabricated poly-Si TFT EEPROM cell is attributed to the ECR N₂O-plasma oxide with good charge-to-breakdown (Qbd) characteristics     

基于柔性PI基底的氧化物IGZO TFT器件工艺及特性研究

讨论了基于柔性PI基底上的底栅型TFT器件工艺,通过工艺优化解决了双层结构干刻速率不同造成的下切角形状。本文TFT器件是基于氧化物IGZO为有源层,栅绝缘层采用Si3N4/SiO2双层结构,采用两次补偿曝光、干刻方式消除干刻引入的下切角形状,有效解决了薄膜沉积引入的断线风险。实验结果表明,经过SEM断面观察,干刻后双层结构taper角度适合TFT器件后续沉膜条件,柔性基底上制作的TFT器件迁移率达到14.8cm2/(V·s),阈值电压Vth约0.5V,亚域值摆幅SS约0.5V/decade,TFT器件的开关比Ion/Ioff106。通过此方法制作出的器件性能良好,满足LCD、OLED或电子纸的驱动要求。     

Process-independent analogue data driver for polysilicon TFT AMLCD

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is very suitable for driving an active matrix LCD (AMLCD) panel as the driver circuit, and the panel can be integrated on the same substrate. This allows the entire display system to be thin and makes the concepts of ‘TV on wall’ and ‘sheet computer’ possible. However, the large variation of threshold voltage of poly-Si TFT across the wafer makes it difficult to obtain analogue amplifiers with constant gain and phase margin. In this paper, an analogue data driver for the poly-Si TFT AMLCD is proposed. An operational amplifier with a gate bias-voltage generation circuit for this analogue data driver, with characteristics independent of variations in threshold voltage, will be presented. In Hspice simulation, with threshold voltage varying from 2.5?V to 4.5?V, gain variations of the proposed amplifier were reduced from ±10?dB to ±0.2?dB and phase margin variations were reduced from 10° to 0.37° compared with typical operational amplifier design. This enables the analogue data driver for AMLCD to be implemented in poly-Si TFT technology.