开态热载流子应力下的n-MOSFETs的氧化层厚度效应

在最大衬底电流条件下(Vg=Vd/2),研究了不同氧化层厚度的表面沟道n-MOSFETs在热载流子应力下的退化.结果表明, Hu的寿命预测模型的两个关键参数m与n氧化层厚度有着密切关系.此外,和有着线性关系,尽管不同的氧化层厚度会引起不同的模型参数,但是如果对于不同厚度的氧化层,采用不同的m与n,Hu的模型仍然成立.在这个结果的基础上,Hu的寿命预测模型能用于更薄的氧化层.     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为4和5nm的n-MOSFETs进行了沟道热载流子应力加速寿命实验,研究了饱和漏电流在热载流子应力下的退化.在饱和漏电流退化特性的基础上提出了电子流量模型,此模型适用于氧化层厚度为4 5nm或更薄的器件.     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

一个超薄氧化物nMOSFET器件的直接隧穿电流经验公式

建立了一个直接隧穿电流的经验公式 .将氧化层厚度作为可调参数 ,用这个经验公式可以很好地拟合超薄氧化物 n MOSFET器件的直接隧穿电流 .在拟合中所得到的氧化层厚度比用量子力学电压 -电容方法模拟得到的氧化层厚度小 ,其偏差在 0 .3nm范围内 .     

热载荷下金属间化合物厚度对焊点可靠性的影响

研究了在热循环载荷条件下,不同厚度的金属间化合物IMC(Intermetallic Compound)层对焊点可靠性的影响。采用Anand本构模型描述无铅焊点在热载荷条件下的粘塑性力学行为,运用有限元模拟电子封装器件在热载荷循环下的应力应变的变化规律,确定关键焊点的位置,得到关键焊点的关键点的应力、应变与时间关系的曲线,分析IMC层厚度与寿命关系曲线,并确定其函数关系。研究表明:在热载荷条件下IMC层厚度越大,其焊点的可靠性越低,寿命越短。在IMC层厚度为8.5μm时,IMC厚度对焊点寿命的影响率出现明显的变化,影响率由–32.8突然增加到–404,当IMC厚度为14.5μm时,焊点的寿命值出现了跳跃。     

PMOS辐照检测传感器总剂量效应模型研究

根据PMOS辐照检测传感器在辐照时所产生的氧化层电荷(Qot)的两个不同模型,模拟计算了不同剂量条件下的亚阈值特性。结果表明,在满足一阶动力学方程下建立的Qot模型与实验结果较为吻合,并适用于更大范围的辐照剂量。此外,还讨论和计算了栅氧化层厚度、沟道掺杂浓度等参数对PMOS辐照检测传感器特性的影响。结果表明,栅氧化层厚度是影响阈值电压漂移量的主要因素。     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

超薄栅MOS器件热载流子应力下SILC的产生机制

通过测量界面陷阱的产生,研究了超薄栅n MOS和p MOS器件在热载流子应力下的应力感应漏电流( SIL C) .在实验结果的基础上,发现对于不同器件类型( n沟和p沟)、不同沟道长度( 1、0 .5、0 .2 75和0 .13 5 μm)、不同栅氧化层厚度( 4和2 .5 nm) ,热载流子应力后的SIL C产生和界面陷阱产生之间均存在线性关系.这些实验证据表明MOS器件减薄后,SIL C的产生与界面陷阱关系非常密切     

Correlation between lifetime, temperature, and electrical stressfor gate oxide lifetime testing

A relationship between the gate oxide lifetime (t_bd), temperature (T), and the electrical stress for the reliability testing is investigated. Based on the various lifetime testing results reported by previous investigators, a new parameter for the oxide lifetime prediction is introduced. The parameter T[log(t_bd)+C], where C is a constant, has a linear relationship with respect to the electrical stress field in the oxide. By using the above parameter, it becomes easy to describe and compare the characteristics of oxide reliability on one graph     

One Method for Fast Gate Oxide TDDB Lifetime Prediction

提出了一种快速推算栅极氧化膜TDDB寿命的新方法.该方法可以用于对工艺的实时监控.通常情况下,为了得到栅极氧化膜在器件使用温度下的TDDB寿命,必须得到三个在一定温度下的不同电压下的TDDB寿命.然后使用一定模型(E模型或者1/E模型)和这个三个寿命推算出氧化膜在器件使用温度下的寿命.比较常用的是E模型.但是为了保证使用E模型推得的寿命的准确性,必须尽量使用较低电压下的寿命来推算想要的寿命.显然,为了获得低电压下的TDDB寿命,必须花费相当长的测试时间(甚至1个月).这对于工艺的实时监控来说,是不能接受的.文中提出一种新的推算栅氧化膜TDDB寿命的方法.运用该方法,可以快速、准确获得栅氧化膜的TDDB寿命,而花费的测试时间不到普通方法的1/1000000.在该方法中,巧妙地同时利用了1/E模型和E模型.     

一种快速推算栅极氧化膜TDDB寿命的方法

提出了一种快速推算栅极氧化膜TDDB寿命的新方法.该方法可以用于对工艺的实时监控.通常情况下,为了得到栅极氧化膜在器件使用温度下的TDDB寿命,必须得到三个在一定温度下的不同电压下的TDDB寿命.然后使用一定模型(E模型或者1/E模型)和这个三个寿命推算出氧化膜在器件使用温度下的寿命.比较常用的是E模型.但是为了保证使用E模型推得的寿命的准确性,必须尽量使用较低电压下的寿命来推算想要的寿命.显然,为了获得低电压下的TDDB寿命,必须花费相当长的测试时间(甚至1个月).这对于工艺的实时监控来说,是不能接受的.文中提出一种新的推算栅氧化膜TDDB寿命的方法.运用该方法,可以快速、准确获得栅氧化膜的TDDB寿命,而花费的测试时间不到普通方法的1/1000000.在该方法中,巧妙地同时利用了1/E模型和E模型.     

Improved prediction of interface-trap generation in NMOST's

Hot-carrier-induced interface-trap generation in NMOSFET's is a serious reliability hazard for CMOS circuits. Its prediction has been either inaccurate or it needed many process dependent fitting parameters. We introduce a new method that improves lifetime prediction by orders of magnitude. Our method requires no additional fitting parameter and is applicable in existing circuit simulators. From the (time dependent) voltages and currents, available in a circuit simulator, we predict the number of generated interface traps. Our prediction method has been checked in more than a hundred experiments on NMOSFET's with 0.2-2.0-μm length, 0.8-10-μm width, and 5.5-25-nm oxide thickness     

Modeling of oxide-charge generation during hot-carrier degradationof PMOSFET's

Oxide-charge generation determines the lifetime for hot-carrier degradation of PMOSFET's. We present a model for the generation of oxide charge and its influences on transistor characteristics. Our model explains the logarithmic time dependence for the generation of oxide charge that is observed systematically for many PMOSFET types. This model is in accordance with an empirical prediction method for PMOSFET degradation that has been published earlier. Furthermore, a relation between the injected charge and the amount of degradation is presented. The paper ends with some applications     

Weibull characteristics of n-MOSFET's with ultrathin gate oxides under FN stress and lifetime prediction

Subthreshold gate voltage shift ΔV_gw of n-MOSFET's with different oxide thicknesses aging at various stress conditions was statisticalized using Weibull distribution. Based on the statistical results, an empirical expression for the relationship between average lifetime and acceleration field was developed, and lifetime predictions were made. Results show that the shape factors (β) of intrinsic failure of the devices with 5.0, 7.0, and 9.0 nm gate oxides under 27 and 105 °C are the same, namely, the mechanisms of the intrinsic failure are the same under low and high temperatures. The proportion of the extrinsic failure increases with temperature increasing. A lifetime prediction method was developed based on the exponential relationship between lifetime and acceleration field. This method can be applied to predict the lifetime of n-MOSFET's with ultrathin gate oxides under FN stress.     

A lifetime prediction method for oxide electron trap damage createdduring hot-electron stressing of n-MOS transistors

Electron trap creation under conditions of hot-electron stress (i.e., stress at V_d=V_g) is examined. It is shown that a relationship exists linking lifetime to the injected gate current and drain current, offering a lifetime prediction method for these types of traps. Comparing this type of damage to interface trap (N_it) creation, it is found that larger energies (approximately 1.5 times that for N_it) are required to generate this defect. It is shown that an extrapolation technique can be used to obtain gate currents at working circuit voltages, extending the prediction of lifetimes for oxide trap creation to low voltages     

Modeling the potential of screen printed front junction CZ silicon solar cell with tunnel oxide passivated back contact

Carrier selective passivated contacts composed of thin oxide, n + polycrystalline Si and metal on top of a n‐Si absorber can significantly lower the recombination current density (J_orear ≤8 fA/cm²) under the contact while providing excellent specific contact resistance (5–10 mΩ‐cm²); 25.1% efficient small area cells with photolithography front contacts on boron doped selective emitter and Fz wafers have been achieved by Fraunhofer ISE using their tunnel oxide passivated contact (TOPCon) approach. This paper shows a methodology to model such passivated contact cells using Sentaurus device model, which involves replacing the TOPCon region by carrier selective electron and hole recombination velocities to match the measured J_orear of the TOPCon region as well as all the light IV values of the cell. We first validated the methodology by modeling a 24.9% reference cell. The model was then extended to assess the efficiency potential of large area TOPCon cells on commercial grade n‐type Cz material with screen‐printed front contacts. To use realistic input parameters, a 21% n‐type PERT cell was fabricated on Cz wafer (5 Ω‐cm, 1.5‐ms lifetime). Modeling showed that the cell efficiency will improve to only 21.6% if the back of this cell is replaced by the above TOPCon, and the performance is limited by the homogenous emitter. Efficiency was then modeled to improve to 22.6% with the implementation of selective emitter (150/20 Ω/sq). Finally, it is shown that screen printing of 40‐µm‐wide lines and improved bulk material (10 Ω‐cm, 3‐ms lifetime) can raise the single side TOPCon Cz cell efficiency to 23.2%. Copyright © 2016 John Wiley & Sons, Ltd.