共查询到18条相似文献,搜索用时 109 毫秒
1.
2.
理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明:边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流. 相似文献
3.
4.
5.
6.
7.
8.
9.
10.
11.
研究了超薄栅氧MOS器件的直接隧穿(direct tunneling,DT)电流模型问题.利用修正的WKB近似方法(modified WKB,MWKB)得到电子隧穿栅氧的几率,利用修正的艾利函数(modified Airy function,MAF)方法计算得到在高电场条件下载流子的量子化能级,从而计算出在不同偏置条件下的DT电流.模型实现了nMOSFET's栅隧穿电流的二维模拟,可以模拟在不同栅漏偏置条件下的器件工作情况,具有较广泛的适用性.通过对比表明,本模型能够与实验结果很好地吻合,且速度明显优于数值方法.利用模型可很好地对深亚微米MOS器件的栅电流特性进行预测. 相似文献
12.
Hao Guan Ming-Fu Li Yandong He Byung Jin Cho Zhong Dong 《Electron Devices, IEEE Transactions on》2000,47(8):1608-1616
The conduction mechanism of the quasibreakdown (QB) mode for thin gate oxide has been studied in a dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide quasibreakdown (QB). Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si-SiO2 interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Twelve Vg, Isub, Isd/ versus time curves and forty eight I-V curves of carrier separation measurements have been demonstrated. All the curves can be explained in a unified way by the LPDR QB model and the proper interpretation of the carrier separation measurements. Particularly, under substrate injection stress condition, there is several orders of magnitude increase of Isub(Isd/) at the onset point of QB for n(p)-MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate, consequently, cold holes are left in the substrate and measured as substrate current. These cold holes have no contribution to the oxide breakdown and thus the lifetime of oxide after QB is very long. Under the gate injection stress condition, there is sudden drop and even change of sign of Isub(Isd/) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate 相似文献
13.
Alessandro Marras Ilaria De Munari Davide Vescovi Paolo Ciampolini 《Microelectronics Reliability》2005,45(3-4):499-506
Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths in the decananometer range: according to the ITRS oxide thickness in the order of 1 nm will be used in 2005 for ultra-short channel CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of direct-tunneling (DT) current on the performance of a wide variety of CMOS circuits is presented. The approach relies on a mixed-mode simulation approach, which allows for predicting the correlation of major performance indices with oxide thickness. 相似文献
14.
15.
Jonghwan Lee Bosman G. Green K.R. Ladwig D. 《Electron Devices, IEEE Transactions on》2002,49(7):1232-1241
An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects 相似文献
16.
The effects of oxygen vacancies on the electronic structure of silicon dioxide and the hole tunneling current were investigated using first-principles calculations. A level related to oxygen vacancy was obtained to be nearly 2.0 eV from the top of valence band within the bandgap of the α-quartz supercell with one oxygen vacancy. And therefore the defect assisted hole (electron) tunneling currents were calculated. The results shows that the hole tunneling current will be dominant for a thinner oxide thickness at low oxide field and the contribution of trap assisted hole tunneling to the total tunneling current decreases with oxide thickness and oxide field increasing. It is concluded that the effects of the oxygen vacancies on the hole tunneling current become smaller with larger oxide thickness and higher electric field. 相似文献
17.
The direct tunneling current through ultra-thin gate dielectrics is modeled by calculating the transmission coefficient of an idealized potential barrier that is modified by the image force. A numerical solution to the Schrödinger equation shows that the barrier lowering induced by image-potential affects the tunneling current largely. An analytical expression for the current is obtained within the Wentel–Kramers–Brillouin approximation. The effects of image force on the direct tunneling current are found to increase with the applied voltage across oxide (Vox) and to decrease with the oxide thickness (Tox). 相似文献
18.
Kuo-Nan Yang Huan-Tsung Huang Ming-Jer Chen Yeou-Ming Lin Mo-Chiun Yu Jang S.S.A. Yu D.C.H. Mong-Song Liang 《Electron Devices, IEEE Transactions on》2001,48(12):2790-2795
This paper examines the edge direct tunneling (EDT) of holes from p+ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness TOX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field EOX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates EOX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once EOX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected 相似文献