共查询到16条相似文献,搜索用时 203 毫秒
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在降压转换器中,为了在不同的负载情况下获得高效率,常采用的方法是在重载时使用脉冲宽度调制(PWM),在轻载时使用脉冲频率调制(PFM),因此需要模式切换信号去控制整个降压转换器的工作状态,同时模式切换信号也可以用于自适应改变功率级电路中的功率管栅宽,减小功率管的栅极电容,提高整体电路的效率。文章设计了一个自适应峰值电流模式切换电路,用于产生模式切换信号,其原理是监控峰值电流的变化,产生峰值电压,将峰值电压与参考电压进行比较,得到模式切换信号,以决定降压转换器是采用PFM模式还是PWM模式。仿真结果表明,在负载电流0.5~500 mA范围内,该电路可以在两种调制模式之间平稳切换,其峰值效率可提升到94%以上。 相似文献
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为了在轻重负载条件下获得更高的转换效率,采用分段式结构和导通电阻更小的NMOS作为输入级,并采用PWM/PFM双调制方式,设计了一种Buck型DC-DC转换器。为解决PWM/PFM调制信号切换问题,采用零电流检测方式进行切换。利用断续导通模式(DCM)和连续导通模式(CCM)下端NMOS管导通时电感电压的不同,检测下端NMOS在导通时电感电压大于零的周期。当电感电压大于零的周期大于2时,则处于DCM模式并自动采用PFM调制模式,关闭一部分功率管以减小开关频率和功率管寄生电容,优化轻载效率;反之则处于CCM模式并采用PWM调制。仿真结果表明,在负载电流10~1 000 mA范围内,该电路可以在两种调制模式平稳切换,在800 mA时峰值效率可提升到96%以上。 相似文献
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设计了一种应用于峰值电流型控制Buck DC-DC转换器的分段式斜坡电流补偿电路,以消除峰值电流控制模式下可能产生的次谐波振荡。该电路采样峰值电流,通过采样电阻将电流转换为电压输出。当开关脉冲控制的导通时间占空比D<35%时,斜坡补偿电压的斜率为零。当占空比D>35%时,斜坡补偿电压的斜率占空比变化。斜坡补偿电路不仅消除了D>50%时次谐波振荡引起的系统不稳定现象,还提高了电源芯片的带载能力。基于0.5 μm BCD工艺进行设计,仿真结果显示,该斜坡补偿电路具有良好的补偿能力和带载能力。应用该电路的DC-DC转换器的最高负载工作电流达到7 A。 相似文献
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设计了一种基于PWM/PFM调制模式的全负载高效率升压型DC-DC转换器。根据负载不同,实现PWM和PFM模式的自动切换。轻载时,进入PFM模式,降低开关损耗,并加入电感峰值限流,减小输出电压纹波。在DCM状态下,利用休眠模式电路,降低静态功耗,同时提出一种抗振铃电路,进一步提升轻载转换效率。芯片实测结果表明,1mA轻载条件下,效率依然达到91.6%,输出电压纹波约为6.6 mV。全负载最高效率可以达到93.1%。 相似文献
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一种PWM/伪PFM双模调制的降压型DC/DC开关电源 总被引:5,自引:1,他引:4
利用根据负载电流的大小变换调制模式的方法实现了一种降压型高转换效率的DC/DC开关电源. 当控制电压占空比小于20%时,采用伪PFM (pseudo-pulse-frequency modulation)模式调制;占空比大于20%时,采用PWM (pulse-width modulation)模式调制,平均转换效率约为90%,输出电流范围为0.01~3.0A. 控制芯片采用0.5μm DPDM CMOS工艺制造,并采用二次集成的方式在封装内部集成了功率p-MOSFET. 相似文献
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This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm2. 相似文献
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Hidekazu Muraoka Osamu Noro Kenya Sakamoto Nabil A.Ahmed Hyun Woo-Lee Mutsuo Nakaoka 《电力电子》2005,3(5):28-32
本文特别针对24V电池输入条件下的低电压、大电流特性,设计了一种新颖的PWM软开关DC-DC前向式功率变换器模型。在局部运行区域,利用了ZCS PWM DC-DC前向式功率变换器的附加控制模式来实现软开关。这种新型功率变换器在低负载条件下可支持PWM-PDM双模控制方式,研究结果证实,在ZCS和有功电压钳位开关条件下,基于PWM-PDM双模控制的软开关前向式功率变换器可在较大的负载范围内改善运行效率。 相似文献
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This paper describes the design of a high speed semiconductor laser diode driver designed for driving 500 mW to 1.5 W diodes at full optical power modulation up to frequencies of 10 MHz. The duty cycle of the modulation may be varied. A switching power-converter based current source allows a higher power delivery efficiency to the diode than in previous designs, allowing for a more modest power supply and dissipation requirements. A dynamic ripple cancellation circuit reduces the power converter output current ripple to less than 1% of full-scale current. The circuit is capable of delivering up to 2.5 A to a laser load, with a 10-90% switching risetime from laser threshold to full on of less than 20 ns 相似文献
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Kejun Wang Changming Pi Wei Yan Wenhong Li 《Analog Integrated Circuits and Signal Processing》2012,71(1):81-94
This paper presents a new method to improve light load efficiency and minimize output ripple of switched-capacitor (SC) DC/DC
converters. In order to improve light load efficiency, this paper proposes adaptive frequency modulation to scale down gate-drive
losses as load current reduces. Adaptive duty cycle modulation is proposed to minimize output ripple as the converter works
under different gain hopping mode. Furthermore, this work optimized switching frequency, the dead time of 2-phase non-overlapping
clocks and switching transistor size for efficiency enhancement. A new compensation circuit is also proposed to make system
stable. A transistor level implementation of the proposed SC converter in Chartered 0.35 μm CMOS process is provided. Measurement
results shows: maximum ripple voltage is <8 mV and efficiency is up to 87%. 相似文献