基于电学法的达林顿管稳态热阻测量方法研究

热阻是功率器件一个重要的热性能参数,影响着结温的高低,同时也用于确定器件结温以及功率器件的安全工作温度范围。每只器件热阻值由于工艺问题有一定偏差,由产品手册无法获得精确热阻值。从电学法测量结温原理出发,以达林顿管BDW47G为试验对象,测量并计算得到其温度系数M=-1.835 8 mV/℃。设计测量电路,并对测量中延迟时间造成的误差进行分析修正,得到达林顿管延迟时间为零时精确结温,最终获得达林顿管稳态热阻的测量计算方法。该方法有助于获得器件关键热性能参数,有助于老炼试验等对结温有要求的试验获得精确结温。     

大功率肖特基SiC二极管热特性研究

基于小电流下肖特基结正向压降的温度特性,建立了温升测量系统。利用该系统对肖特基SiC二极管的瞬态温升进行了测量,结果显示瞬态温升曲线呈阶梯状变化。利用结构函数的方法对瞬态温升曲线进行处理,分析了肖特基SiC二极管在热流传输路径上的热阻构成。研究了三引脚封装的肖特基SiC二极管在相同大功率的条件下,两正极引脚单独使用和并联使用时的热阻特性,结果显示,在两正极引脚并联使用时,其热阻比单独作用时减少一半,这表明三引脚封装的肖特基SiC二极管的两个正极是并联的,并共用一个负极和散热片。     

基于NI DAQ的功率LED热特性测量分析系统

分析了功率发光二极管(LED)基于电学测量的热阻的测量方法,介绍了采用高性能数据采集卡构建了新型的功率LED热特性自动测量分析系统,实现对功率LED结温和热阻的精确、简便的测量.对几种典型功率LED样管的测试结果,与校正样品的标称值完全相符,并可对LED的瞬态热过程进行更深入分析.     

热阻的概念和测试方法

热阻是半导体器件的基本特性和重要参数指标，阐述了（稳态）热阻和瞬态热阻定的定义，热阻与电流的关系、附加热阻和平板形器件总热阻公式推导等概念。     

瞬态热阻测试在贴片二极管在线测试中的应用

表面贴装整流极管的焊接质量直接影响其可靠性.提出了通过测试与瞬态热阻等价的热敏电压增量来评价焊接质量、筛选焊接不良的产品.利用TRR8000测试仪对样品进行合适条件下的在线筛选,能够有效剔出焊接不良产品,提高表面贴装整流二极管的可靠性.     

双极晶体管ΔV_(be)瞬态热阻测试法精度修正

对双极型晶体管ΔVBE瞬态热阻测试法中晶体管壳温波动和测量延迟时间的误差进行了分析,提出了提高测试精度的误差修正方法.以3DK457(F0金属封装)双极晶体管为实验对象进行了研究,结果表明:晶体管瞬态热阻ΔVBE修正测试方法与红外扫描热像法和标准电学法相比较在保持较高测量精度的前提下,测试成本低,测量效率高.     

双极晶体管△Vbe瞬态热阻测试法精度修正

对双极型晶体管△VBE瞬态热阻测试法中晶体管壳温波动和测量延迟时间的误差进行了分析,提出了提高测试精度的误差修正方法.以3DK457(F0金属封装)双极晶体管为实验对象进行了研究,结果表明:晶体管瞬态热阻△VBE修正测试方法与红外扫描热像法和标准电学法相比较在保持较高测量精度的前提下,测试成本低,测量效率高.     

利用结构函数分析功率型LED的热特性

运用电学法测量功率型LED冷却瞬态温度曲线,通过数学方法将其转化为积分和微分结构甬数来分析器件各区域的热阻和热容.结果发现,各层材料的测量值与理论值基本一致.1μs的瞬态数据采集精度和高的重复性保证了实验结果的准确性和可靠性,运用这种方法比较了3种不同金属芯印刷电路板(MCPCB)对功率型LED的散热效果,贝格斯Al基板散热性能最好,ANT Al基板次之,普通Al基板最差.研究表明,利用结构函数分析功率型LED的热特性是一种强有力的方法.     

LED热学性能测试方法的研究综述

LED是21世纪最具发展前景的照明光源之一。散热是限制功率型LED器件广泛应用的主要瓶颈,精确的热学测量则是有效热管理的重要前提。目前对于LED热学性能的测量方法研究主要有红外热成像法、电学参数法、瞬态热测试法、光谱法、光功率法等方法。从LED热学特性及热学参数测试的基本原理出发,综述了国内外关于LED热学性能的测试方法研究,分析比较了各方法测量LED热阻的优缺点,讨论了各自的适用范围。瞬态热测试法由于其测试精度高、可测热结构函数等优点,具有重要的研究价值和良好的应用前景。     

大脉宽微波功率组件瞬态热阻的新型计算方法

微波功率组件通常在脉冲条件下工作,当脉宽时间超过芯片响应时间时,传统基于线性叠加原理的瞬 态热阻计算方法将导致结果显著偏小。根据微波功率组件脉冲均一重复的特征,结合组件瞬态升温曲线,文中提出了 一种求解隐式方程的新型瞬态热阻计算方法。对比发现,在所有脉宽范围内新方法的计算精度均高于传统方法,尤其 在大脉宽条件下更明显。该方法适用性广,可用于其它脉冲式工作电子设备(如激光器、电源等)的瞬态热阻计算。     

Reverse bipolar transistor conduction in high-current PWM inverters

Most PWM (pulse width-modulated) inverters using bipolar transistors experience the problem of reverse transistor conduction. This effect is analyzed for various types of base drives. It is shown to be the most serious for low-impedance direct drives. A model is developed for this case and verified experimentally. Problems associated with turn-on and turn-off in the reverse conduction mode are investigated. Various base drives, including both direct drives and Darlington configurations, are analyzed. Reverse transistor conduction is found to have the most serious implications for transistors driven directly by a low impedance source. Although discrete devices are discussed, the results also apply to integrated Darlington modules     

测量大功率LDMOS晶体管特性的TRL校准方法研究

The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths.An improved thru-reflect-line(TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented.According to the TRL algorithm,the individual two-port S parameters of each fixture half can be obtained.By de-embedding these S parameters of the test fixture,an accurate calibration can be made.The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width.The impedance of the transistor is obtained,and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density.From the results,it is seen that the presented TRL calibration algorithm works well.     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible     

Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing

One of the effective techniques to reduce leakage power is power gating. Previously, a Distributed Sleep Transistor Network was proposed to reduce the sleep transistor area for power gating by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current flowing through sleep transistors. In this paper, we propose a new methodology for determining the sizes of sleep transistors of the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop and minimizing the sizes of sleep transistors. We also present mathematical proofs of our theorems and lemmas in detail. Our experimental results show 23.36% sleep transistor area reduction compared to the previous work on average.      

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

晶体管红外热像图的热谱分析方法

使用自编的分析软件，根据比色法对所摄取的晶体管红外热像图进行了热谱分析，给出了晶体管发射区热谱和发射区一维温度分布曲线．一维温度分布曲线给出了整个发射区的结温分布情况，并可直接读取发射区的峰值结温和最低结温，还可以计算出平均结温．晶体管热谱是表示晶体管结温不均匀性的一种与热像图不同的新方法．     

晶闸管的瞬态热阻抗及其结温温升的研究

系统地阐述了晶闸管的瞬态热阻抗 ,针对晶闸管承受不同的功率脉冲 ,利用不同的计算方法计算瞬态热阻抗值 ,从而确定结温温升 ,并比较了它们的原理、精度及其应用范围。特别是利用了一种新的瞬态热阻抗计算模型 ,当晶闸管承受持续时间极短且周期、占空比均变化的任意波形功率脉冲时 ,它能够比较精确地分析晶闸管的热特性 ,计算半导体结的最大温升     

Intermodulation distortion of a bipolar common-emitter amplifier with arbitrary emitter impedance and input matching network

In this paper, concise formulas for the intermodulation distortion of a bipolar common-emitter amplifier stage with arbitrary emitter impedance and input matching network are presented. These expressions provide quantitative insight in the influence of transistor properties, emitter degeneration and input power matching on distortion. Only a small set of measurable transistor parameters is needed. As examples, IIP3 is calculated for transistor only, transistor with emitter inductance, and transistor with emitter inductance and input matching circuit. Two transistors are compared: a double-poly Si transistor and a SiGe transistor in a similar process. A good agreement between analytical and numerical results is obtained.     

LF Dependence of the output admittance in short-channel n- or p-power MOS transistors

This paper presents the output admittance properties of p-or n-type short-channel power MOS transistors operating beyond pinch-off, in the low-frequency (LF) range. In the Nyquist chart, it appears that the signs and amplitudes of the real and imaginary parts of the output admittance are bias dependent. These properties are accounted for by taking into account the internal feedback between the electrical mechanisms and the thermal phenomena. A theoretical expression of the admittance is proposed and compared to the experimental results. A method for determining the thermal impedance and the equivalent circuit of an MOS transistor is inferred from this analysis.     

A time-domain method for the analysis of thermal impedance responsepreserving the convolution form

The study of the thermal behavior of complex packages such as multichip modules (MCMs) is usually carried out by measuring the so-called thermal impedance response, that is: the transient temperature after a power step. From the analysis of this signal, the thermal frequency response can be estimated, and consequently, compact thermal models may be extracted. We present a method to obtain an estimate of the time constant distribution underlying the observed transient. The method is based on an iterative deconvolution that produces an approximation to the time constant spectrum while preserving a convenient convolution form. This method is applied to the obtained thermal response of a microstructure as analyzed by finite element method as well as to the measured thermal response of a transistor array integrated circuit (IC) in a SMD package