适用于D类音频功放的PWM高速比较器设计

设计了一种应用于CMOS D类音频功率放大器的PWM高速比较器。输入级为Rail-to-Rail结构,中间级由锁存器和自偏置差分放大器组成,输出级为反相器结构。由于采用了锁存器和自偏置放大器结构,比较器可以在很短的时间内驱动大电容,满足后续电路对驱动能力的要求。基于CSMC 0.5μm CMOS工艺的BSIM3V3Spice模型,采用Hspice对PWM比较器进行仿真。结果表明,在典型模型下,比较器的电源抑制比为56dB,直流开环增益为45dB,输入共模范围(ICMR)为-0.19～4.93V,传输延时为15ns。     

一种高效率 PWM CMOS D类音频功率放大器

基于反馈系统的闭环结构,采用全差分前置放大和全差分反馈结构,提出了一种高效率PWM CMOS D类音频功率放大器,并采用一种具有滞回结构Rail-to-Rail比较器作为PWM比较器,以保证良好的噪声性能。整个电路基于CSMC 0.5μm CMOS工艺进行实现,最大转换效率达到90％,电源电压范围为2.5-5.5V,1kHz下的THD+N小于0.20％,电源抑制比为-75dB,空载消耗电流为2.8mA,待机电流为0.5μA,有效芯片面积为1.47mm*1.52mm,最大功率可以达到2.5W,能应用于各种高效率中小功率音频放大系统。     

CMOS PWM D类音频功率放大器的过流保护电路

基于Class-D音频功率放大器的应用,采用失调比较器及单边迟滞技术,提出了一种过流保护电路,其核心为两个CMOS失调比较器。整个电路基于CSMC0.5μmCMOS工艺的BSIM3V3Spice典型模型,采用Hspice对比较器的特性进行了仿真。失调比较器的直流开环增益约为95dB,失调电压分别为0.25V和0.286V。仿真和测试结果显示,当音频放大器输出短路或输出短接电源时,过流保护电路都能正常启动,保证音频放大器不会受到损坏,能完全满足D类音频放大器的设计要求。过流保护电路有效面积为291μm×59.5μm。     

一种高效2.1声道D类音频功放设计

基于CSMC 0.5μm DPDM CMOS工艺,实现了一种具有2.1声道的D类音频功率放大器的设计,该功放由一个全桥差分输出结构的重低音功率放大器和两个半桥单端输出结构的立体声功率放大器构成。详细介绍了2.1声道D类音频功放的整体结构、前置运算放大器和轨至轨比较器的电路设计。仿真和测试结果表明:在电源电压5 V,该功放可向3Ω负载电阻提供2.5 W+0.6 W×2的输出功率;在电源电压3～6 V范围内,最大转换效率可达90%以上;重低音通道的总谐波失真与噪声之和小于0.7%,立体声通道的总谐波失真与噪声之和小于1%。     

基于0.8μm BCD工艺的20W×2集成D类音频功放设计

基于0.8μm BCD工艺完成了一种具有高转换效率的20W×2立体声集成音频功率放大器.该放大器可在18V电源电压下以全桥输出的方式向8Ω负载提供超过20W的功率,其转换效率可达85%以上.介绍了功率输出级、过流保护电路以及高性能轨-轨比较器的设计,并基于横向双扩散MOSFET器件结构讨论了功率输出器件寄生效应对输出电压波形失真的影响.最后给出了所设计的D类音频功率放大器的测试结果.     

基于0.8μm BCD工艺的20W×2集成D类音频功放设计

基于0.8μm BCD工艺完成了一种具有高转换效率的20W×2立体声集成音频功率放大器.该放大器可在18V电源电压下以全桥输出的方式向8Ω负载提供超过20W的功率,其转换效率可达85%以上.介绍了功率输出级、过流保护电路以及高性能轨-轨比较器的设计,并基于横向双扩散MOSFET器件结构讨论了功率输出器件寄生效应对输出电压波形失真的影响.最后给出了所设计的D类音频功率放大器的测试结果.     

高线性度CMOS射频AB类功率放大器设计

CMOS射频AB类功率放大器广泛应用于单片集成无线芯片内.采用恒定最大电流的方法对其效率进行分析,采用归一化输入电压的方法对其线性度进行分析.利用AB类功率放大器系统增益的非线性与CMOS跨导非线性相互补偿,提高了CMOS射频AB类放大器的线性度.基于TSMC 0.18μm CMOS混合信号工艺,设计了一款两级射频AB类功率放大器.该射频功率放大器差动输入,单端输出,工作频段为804~940MHz,工作电压为3V.仿真指标为:增益为11dB,输出1dB压缩点为17.2dBm,OIP3为18.2dBm,附加效率为37%.     

恒定跨导Rail-to-Rail CMOS运放设计

设计了一种新型的低电压低功耗且跨导恒定的Rail-to-Rail CMOS运算放大器,输入级采用改进的最大电流选择电路结构,输出级采用推挽输出结构,其输入输出摆幅均为Rail-to-Rail,工作电压为±1.5V.整个电路采用BSM30.5μm CMOS工艺模型参数进行了HSPICE仿真,静态功耗仅为0.5mW,当电路驱动20pF的电容负载时,电路的直流增益达到78dB,单位增益带宽达到470MHz,相位裕度为59°.     

一种用于液晶显示源驱动的放大器设计

设计出一种用于TET液晶显示的源驱动放大器.放大器的输入级采用互补差分对形式,输出级则采用甲乙类CMOS结构,实现了输入输出的Rail-to-Rail.增加了平衡电路,抑制了非线性.通过设置合适的电压偏置和小的偏置电流在5V工作电压下实现了低功耗.在-40～85℃范围内,基于和舰0.25μm高压CMOS工艺,采用HSPICE仿真验证,在30pF负载电容条件下,放大器的静态功耗仅有19μW,输出电压范围为0V～5V,开环电压增益达到132dB,总谐波失真仅为0.009%.能很好满足液晶显示源驱动电路的要求,并成功应用于LCD驱动芯片中.     

D类功放中高性能三角波积分器的设计

设计了一款应用于音频D类功率放大器中的积分器,用于产生PWM调制所需的三角波信号,积分器内部高增益、宽输出摆幅的高速运放大大提升了积分器的性能,有效地提高了D类功放的效率,本设计基于0.6μmBCD工艺,经Cadence环境仿真验证,内部运放开环增益高达103dB,单位增益带宽达到6.8MHz,而且压摆率不受限制;积分器输出三角波中心电平稳定在3V,且摆幅高达5V.     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

一种高性能Class D音频放大器PWM控制的设计

文中设计了一种应用于Class D音频放大器中高性能PWM控制。该控制能够在较宽的电源电压范围内,使调制锯齿波的输入电平及音频输入信号经过前置放大后的共模电平跟随电源电压的变化而变化。共模电平经过PWM比较器得到占空比随输入信号变化的控制信号,从而提高系统的输出功率。仿真结果显示,当电源电压在2．4-5V范围变化时．音频信号和调制锯齿波的共模电平偏差在2mV以内,同时锯齿波的幅度也随着电源电压的升高而升高．显示了良好的线性跟随性。     

Digital correction of PWM switching amplifiers

Pulsewidth modulated (PWM) signals for driving a switching audio amplifier can be synthesized in the digital domain with extremely high linearity and precision. However, nonidealities associated with the power stage degrade output performance. A method to digitally correct for these nonidealities, resulting in very low total harmonic distortion (THD) and high signal-to-noise ratio (SNR) performance, is presented. This method also provides excellent rejection of power supply noise which is otherwise absent in digital PWM amplifiers. To meet noise requirements for hi-fi audio, the feedback structure is a fourth-order structure which shapes the noise beyond the audio band. The method has been implemented on a bread board, and state-of-the-art performance was achieved. Total harmonic distortion of 85 dB and dynamic range of 100 dB was measured using Audio Precision test equipment.     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。     

适用于D类音频功放的动态迟滞PWM比较器

系统介绍了基于PWM（Pulse Width Modulation）调制的D类音频功率放大器的原理及特点。针对传统比较器迟滞固定的不足,通过引入两路电流反馈,设计了一种新颖的动态迟滞PWM比较器。同等分辨率下,其抗噪声能力远好于传统的比较器。电路的设计基于TSMC 0.6umBCD工艺。Spectre仿真结果表明,在载波以及输出的不同状态下,比较器的迟滞在20mV与80mV之间切换,并且其增益高达79dB,单位增益带宽大于10MHz。     

2.5W低噪声CMOSD类音频功放设计

提出了一种基于0.5μm5VCMOS工艺的低噪声PWM调制D类音频功率放大器。该放大器在5V电源电压下以全桥方式可以驱动4Ω负载输出2.5W功率;转换效率等于87%,信噪比达94dB(负载8Ω,输出功率1W);THD+N仅0.05%(负载4Ω,输出功率1W);PSRR为68dB(频率1kHz)。分析了整体电路结构及其线性化模型,并着重介绍了高性能前置斩波稳定运算放大器(开环增益117dB,等效输入噪声16μV.Hz-1/2),线性三角波振荡电路(斜率偏差仅±0.2%)和功率器件、驱动电路的设计。最后给出了D类放大器的测试结果。     

一种用于音频系统的1.1mW 87dB动态范围的ΔΣ调制器

本文描述了一款应用于音频系统的1.1mW 87dB动态范围的 Delta-Sigma 调制器的设计,设计采用0.18um CMOS工艺。由于采用带有前馈支路的多比特结构,第一级积分器的输出摆幅得到有效压缩。第一级积分器采用结构简单,直流增益仅34dB,工作在1V电压下的电流镜型跨导放大器。在3KHz信号输入下,该调制器可在100Hz~24KHz的频率范围内达到83.8dB的峰值SNDR和87dB的动态范围。     

A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third order AS modulator implemented in 0.18 μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process     

A current-mode power sigma-delta modulator for audio applications

Linear and switching techniques are currently adopted to implement current-mode power stages. Pulsewidth modulation (PWM) is usually employed with the switching technique for both industrial and audio applications. In this paper, the Sigma-Delta modulation is considered as an alternative to the PWM in devising a switching current-mode power stage suitable for audio amplification. The proposed modulator is analyzed and simulated. The whole system was realized on an experimental breadboard. The results carried out on the prototype are reported and discussed. The electrical characterization presents interesting features in terms of linearity, noise, and power efficiency.