A 18-mW,20-MHz bandwidth,12-bit continuous-time∑△modulator using a power-efficient multi-stage amplifier

正A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth,implemented in 130nm CMOS technology is presented.The modulator is comprised of an active-RC operational-amplifier based loop filter,a 4-bit internal quantizer and three current steering feedback DACs.A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter.Non-return-to -zero DAC pulse shaping is utilized to reduce clock jitter sensitivity.A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy,avoiding the use of a dynamic element matching algorithm to induce excess loop delay.The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio,and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

An A/D interface based on ΣΔ modulator for thermal vacuum sensor ASICs

A new Σ Δ modulator architecture for thermal vacuum sensor ASICs is proposed. The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 10⁵ Pa. The amplified differential output voltage signal of the sensor feeds to the Σ Δ modulator to be converted into digital domain. The presented Σ Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity. Compared with other feed-forward architectures presented before, the circuit complexity, chip area and power dissipation of the proposed architecture are significantly decreased. The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise. The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz. The circuit has been fabricated in a 0.5 μ m 2P3M standard CMOS technology. It occupies an area of 5 mm² and dissipates 9 mW from a single 3 V power supply. The performance of the modulator meets the requirements of the considered application.     

A fourth-order bandwidth-reconfigurable delta-sigma modulator for audio applications

正A single loop fourth-order delta-sigma modulator is presented for audio applications.A reconfigurable mechanism is adopted for two bandwidth-based modes(8 kHz/16 kHz).Manufactured in the SMIC 0.13μm CMOS mixed signal process,the chip consumes low power(153.6μW) and occupies a core area of 0.98×0.46 mm~2.The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode,as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode.The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.     

Continuous time sigma delta ADC design and non-idealities analysis

A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS.A detailed non-idealities analysis(excess loop delay,clock jitter,finite gain and GBW,comparator offset and DAC mismatch) is performed developed in Matlab/Simulink.This design is targeted for wide bandwidth applications such as video or wireless base-stations.A third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier -based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency.The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16.The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.     

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2.     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

一种用于微机械惯性传感器中的16位ΣΔ调制器

A fourth-order low-distortion low-pass sigma-delta （∑△） modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio （SNR） of 100 dB and dynamic range （DR） of 103 dB at an oversampling rate （OSR） of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.     

一款应用于生物传感器的1.2V-600nW 12bit 2kS/s的增量型模数转换器

This paper presents an ultra-low power incremental ADC for biosensor interface circuits.The ADC consists of a resettable second-order delta–sigma(°/ modulator core and a resettable decimation filter.Several techniques are adopted to minimize its power consumption.A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators.A correlated-double-sampling(CDS)technique is applied to reject the offset and 1/f noise,thereby removing the integrator leakage and relaxing the gain requirement of the OTA.A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply.The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators.The capacitors used in this design are of customized metal–oxide–metal(MOM) type to reach the minimum capacitance set by the k T =C noise limit.Fabricated with a 1P6 M 0.18 m CMOS technology,the presented incremental ADC consumes600 n W at 2 k S/s from a 1.2 V supply,and achieves 68.3 d B signal to noise and distortion ratio(SNDR) at the Nyquist frequency and an FOM of 0.14 p J/conversion step.The core area is 100120 m2.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

正A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm~2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_(1dB) better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

一个1.2伏CMOS0.13微米工艺19.2毫瓦10位30兆采样率流水线模数转换器

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented. For the sake of lower power and area, the pipelined stages are scaled in current and area, and op amps are shared between the successive stages. The ADC is realized in the 0.13-μ m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range, poor analog characteristic devices, the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference. Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio, 67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal. The FoM is 0.33 pJ/step. The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB, respectively. The ADC core area is 0.94 mm².     

A widely tunable fiber ring laser with closed loop control based on high-precision stepper motor

A tunable single-longitudinal mode erbium-doped fiber ring laser based on stepper motor and closed loop control is proposed and demonstrated. The system consists of an erbium-doped fiber (EDF), a tunable fiber Bragg grating (FBG) filter and a wavelength detector. The characteristics of output laser, such as output power, power stability and 3-dB linewidth, are investigated in the operation range of 1 531—1 569 nm. The repeated experimental results of the fiber laser show that the 3-dB linewidth is less than 17 ps, the side-mode suppression ratio (SMSR) is up to 60 dB, the output power is up to 1.37 dBm, and the power variation is less than 0.61 dB.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

一种应用于RFID标签的新型功率放大器设计

A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm² in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

一种采用PVT不敏感电荷传输电路的27mW 10位125MSPS 电荷域流水线模数转换器

A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm~2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.     

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For power optimization,the voltage supply of the digital part is lowered,and the offset voltage of the latch is self-calibrated.Targeted for better linearity and lower noise,an improved digital-to-analog converter capacitor array layout strategy is presented,and a low kick-back noise latch is proposed.The chip was fabricated by using 0.18μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only,resulting in a figure of merit of 220 fJ/conversion-step.The ADC core occupies an active area of only 674×639μm~2.     

Low-power switched-capacitor delta-sigma modulator for EEG recording applications

This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram(EEG) monitoring applications.To reduce the power consumption,the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure.The modulator is designed in a 0.35-μm 2P4M standard CMOS process,with an active area of 365×290μm~2.Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 ...     

一种用于热电堆传感器检测的55dB SNDR, 2.2mW 的双斩波稳定模拟前端电路

A double chopper-stabilized analog front-end （DCS-AFE） circuit for a thermopile sensor is presented, which includes a closed-loop front-end amplifier and a 2nd-order 1 bit quantization sigma-delta modulator. The amplifier with a closed-loop structure ensures the gain stability against the temperature. Moreover, by adopting the chopper-stabilized technique both for the amplifier and 2nd-order 1-bit quantization sigma-delta modulator, the low-frequency 1/f noise and offset is reduced and high resolution is achieved. The AFE is implemented in the SMIC 0.18 μm 1P6M CMOS process. The measurement results show that in a 3.3 V power supply, 1 Hz input frequency and 3KHz clock frequency, the peak signal-to-noise and distortion ratio （SNDR） is 55.4 dB, the effective number of bits （ENOB） is 8.92 bit, and in the range of -20 to 85 degrees, the detection resolution is 0.2 degree.     

一款便携式移动应用的低成本超高频无源射频识别读写器收发机芯片设计

A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.