对数跳跃加法器的静态CMOS实现

介绍了一种32位对数跳跃加法器结构.该结构采用EL M超前进位加法器代替进位跳跃结构中的组内串行加法器,同EL M相比节约了30 %的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用L ing算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现“与-异或”功能;1.0 μm CMOS工艺实现的32位对数跳跃加法器面积为0 .6 2 mm2 ,采用1μm和0 .2 5 μm工艺参数的关键路径延迟分别为6 ns和0 .8ns,在10 0 MHz下功耗分别为2 3和5 .2 m W.     

64位整数加法器的设计与实现

为了提高算术逻辑部件的性能,采用多米诺逻辑和偏斜逻辑门的电路结构,结合并行前缀加法器的优点,设计实现了一款64位高性能整数加法器.根据需要,设计了一种符号扩展电路,使之能够处理带符号操作数的加减法,符号扩展结果可以进行溢出判断.模拟结果表明:在0.13μm CMOS的工艺条件下,关键路径的延时为630ps功耗为21.6 mW,达到了高速低功耗的设计目标.     

对数跳跃加法器的静态CMOS实现

介绍了一种32位对数跳跃加法器结构.该结构采用ELM超前进位加法器代替进位跳跃结构中的组内串行加法器,同ELM相比节约了30%的硬件开销.面向该算法,重点对关键单元进行了晶体管级的电路设计.其中的进位结合结构利用Ling算法,采用支路线或电路结构对伪进位产生逻辑进行优化;求和逻辑的设计利用传输管结构,用一级逻辑门实现"与-民或"功能;1.0μm CMOS工世实现的32位对数跳跃加法器面积为0.62mm2,采用1μm和0.25μm 工世参数的关键路径延迟分别为6ns和0.8ns,在100MHz下功耗分别为23和5.2mW.     

三值绝热多米诺加法器开关级设计

通过对绝热多米诺电路和加法器的研究,该文提出一种新颖低功耗三值加法器的开关级设计方案。该方案首先利用开关-信号理论,结合绝热多米诺电路结构特点,推导出三值加法器本位和电路与进位电路的开关级结构式,由此得到一位三值加法器单元电路;然后通过单元电路的级联得到四位三值绝热多米诺加法器;最后,利用Spice软件对所设计的电路进行模拟,结果显示所设计的四位三值绝热多米诺加法器具有正确的逻辑功能,与四位常规多米诺三值加法器相比,能耗节省约61%。     

一种自定时的前置进位加法器设计

从时序控制的角度出发,研究提高加法器性能的方法。在研究前置进位加法器的算法和结构后,又对多米诺电路的时钟控制技术进行深入分析。结合前置进位结构和自定时时钟控制．设计了一个32b多米诺加法器。该加法器能有效地提高时钟使用率。在TSMC0．18um工艺下,加法器的最大延时为970ps,约为相同工艺下13倍FO4的延时。     

能量回收阈值逻辑电路

通过把阈值逻辑应用在能量回收电路中,提出了一种新的电路形式——能量回收阈值逻辑电路(energyre-coverythresholdlogic,ERTL).阈值逻辑的应用,使ERTL电路的门复杂度大大降低,同时进一步降低了功耗.分别以ERTL电路和静态CMOS电路设计了4位超前进位加法器,两个加法器采用相同的结构.ERTL加法器逻辑电路的晶体管数目只占静态CMOS加法器的63%,与现有的能量回收电路相比,硬件开销减少.设计使用的是TSMC0.35μm工艺,分别在3V和5V工作电压下对电路进行Spice仿真.仿真结果显示,在实际的工作负载和工作频率范围内,ERTL电路的能耗只有静态CMOS电路的14%～58%     

改进结构的64位CMOS并行加法器设计与实现

介绍了一个用于高性能的微处理器和DSP处理器的快速64位二进制并行加法器.为了提高速度,改进了加法器结构,该结构大大减少了加法器各级门的延迟时间.基于改进的加法器结构,有效地使用动态复合门、时钟延迟多米诺逻辑和场效应管尺寸缩小技术,可以取得良好的电路性能.该加法器采用UMC 2.5V 0.25μm 1层多晶5层金属的CMOS工艺实现.完成一次加法运算的时间是700ps,比传统结构的加法器快20%;面积和功耗分别是0.16mm2和200mW@500MHz,与传统结构加法器相当.     

能量回收阈值逻辑电路

通过把阈值逻辑应用在能量回收电路中,提出了一种新的电路形式--能量回收阈值逻辑电路(energy recovery threshold logic,ERTL).阈值逻辑的应用,使ERTL电路的门复杂度大大降低,同时进一步降低了功耗.分别以ERTL电路和静态CMOS电路设计了4位超前进位加法器,两个加法器采用相同的结构.ERTL加法器逻辑电路的晶体管数目只占静态CMOS加法器的63%,与现有的能量回收电路相比,硬件开销减少.设计使用的是TSMC 0.35μm工艺,分别在3V和5V工作电压下对电路进行Spice仿真.仿真结果显示,在实际的工作负载和工作频率范围内,ERTL电路的能耗只有静态CMOS电路的14%～58%.     

一种使用Advance MS的全定制加法器加速设计

采用一种加速全定制IC设计的方法,完成了基于CSMC(华润上华)0.5 μm工艺的32位加法器的设计.使用动态差分多米诺逻辑,实现了基于Brent-Kung树结构的超前进位加法器;采用Mentor Graphics Advance MS仿真软件,加速进行Spice网表的仿真和版图后仿.仿真结果验证了Spice网表的正确性,得出加法器在版图后仿的关键路径延时为4.62 ns,整个设计流程可以应用于其他一些重要核心单元的全定制设计.     

对数跳跃加法器的算法及结构设计

本文介绍一种新型加法器结构——对数跳跃加法器,该结构结合进位跳跃加法器和树形超前进位加法器算法,将跳跃进位分组内的进位链改成二叉树形超前进位结构,组内的路径延迟同操作数长度呈对数关系,因而结合了传统进位跳跃结构面积小、功耗低的特点和ELM树形CLA在速度方面的优势.在结构设计中应用Ling's算法设计进位结合结构,在不增加关键路径延迟的前提下,将初始进位嵌入到进位链.32位对数跳跃加法器的最大扇出为5,关键路径为8级逻辑门延迟,结构规整,易于集成.spectre电路仿真结果表明,在0.25μmCMOS工艺下,32位加法器的关键路径延迟为760ps,100MHz工作频率下功耗为5.2mW.     

Monte Carlo analysis of a low power domino gate under parameter fluctuation

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.     

参数浮动下低功耗多米诺门的蒙特卡罗分析

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique （DTV） in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.     

Dynamic current testing for CMOS domino circuits

In this paper, we propose a method for testing CMOS domino circuits using the transient power supply current. The method is based on monitoring and processing the transient current. We evaluate the effectiveness of this testing method through simulations of various domino circuits of different sizes. Moreover, we propose a normalising technique to mask the process variations effect associated with current testing. Furthermore, we present a test vector generation algorithm for testing large domino circuits, and develop and implement a clustering technique to improve the fault coverage of the test method when used with large circuits. The clustering algorithm divides the circuit into different clusters where each cluster is fed by a different power supply branch.     

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.Kye-Shin Lee received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1992 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas.He was with LG Semicon Co. (now Hynix Semicon Inc.), Seoul, Korea from 1994 to 1999, where he was involved in mixed signal circuit design and testing of BW/Color CCD chipsets including timing/sync. signal generator, camera signal processor, USB camera interface, and sigma-delta CODECs for audio and voice band applications. His research has been focused on switched-capacitor circuits, sigma-delta modulators, and pipeline ADCs.Yunyoung Choi received the B.S. degree from Kwangwoon University, Seoul, Korea, in 1999 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas. He worked for Texas Instruments, Dallas, from May to December 2003 at the Wireless Business Unit. His research interest includes sigma-delta A/D and D/A converters for audio systems and RF applications.Franco Maloberti received the Laurea Degree in physics (summa cum laude) from the University of Parma, Parma, Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico, in 1996.In 1993, he was a Visiting Professor at ETH-PEL, Zurich, Switzerland. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group, University of Pavia, Pavia, Italy, and the TI/J.Kilby Analog Engineering Chair Professor at Texas A&M University, College Station. He is currently with the University of Pavia and an adjunct Professor at the University of Texas at Dallas. His professional expertise is in the design, analysis, and characterization of integrated circuits and analog digital applications, mainly in the area of switched-capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A/D design. He has written more than 250 published papers, three books, and holds 15 patents.Dr. Maloberti was a 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institution of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS triode transistor transconductance for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects’ Evaluator and Reviewer and as a European Union expert in many Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs’ evaluator. He was Vice-President, Region 8, of the Editor of IEEE Circuits and Systems (CAS) Society from 1995 to 1997 and an Associate Editor of the IEEE Transcations on Circuits and Systems II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millennium Medal. He is the President of IEEE Sensors Council and a member of the Board of Governors of the IEEE CAS Society. He is also the member of the Italian Electrotechnical and Electronic Society (AEI) and the Editorial Board of Analog Integrated Circuits and Signal Processing.     

45nm CMOS工艺下的低泄漏多米诺电路研究

在研究了45nm CMOS工艺下晶体管泄漏电流特性的基础上,提出了一种可以同时减小多米诺逻辑电路亚阈值和栅极氧化层泄漏功耗,带有NMOS睡眠开关并使用双阈值电压、双栅极氧化层厚度的电路技术。该电路技术与标准的双阈值电压多米诺逻辑电路相比,待机模式时消耗的总泄漏功耗在110℃时最高可以减小65.7%,在25℃时最高可以节省达94.1%。     

高性能微处理器中一种改进的高扇入多米诺电路设计与实现

设计实现了一种改进的高扇入多米诺电路结构.该电路的nMOS下拉网络分为多个块,有效降低了动态节点的电容,同时每一块只需要一个小尺寸的保持管.由于省去了标准多米诺逻辑中的尾管,有效地提升了该电路的性能.在0.13μm工艺下对该结构实现的一个64位或门进行模拟,延迟为63.9ps,功耗为32.4μw,面积为115μm2.与组合多米诺逻辑相比,延迟和功耗分别降低了55%和38%.     

高性能微处理器中一种改进的高扇入多米诺电路设计与实现

设计实现了一种改进的高扇入多米诺电路结构. 该电路的nMOS下拉网络分为多个块,有效降低了动态节点的电容,同时每一块只需要一个小尺寸的保持管. 由于省去了标准多米诺逻辑中的尾管,有效地提升了该电路的性能. 在0.13μm工艺下对该结构实现的一个64位或门进行模拟,延迟为63.9ps,功耗为32.4μW,面积为115μm2. 与组合多米诺逻辑相比,延迟和功耗分别降低了55%和38%.     

高速抗噪声CMOS动态电路设计

提出了一种利用窄脉冲发生器驱动输出级,以提高电路抗噪声能力,同时保持动态电路的高速特性的多输入动态逻辑电路.提出了这种电路的分析模型,用于说明电路的抗噪声特性和管子的参数设置.在0.18μm CMOS工艺,1.8V的Vdd电压和55℃的环境温度下,模拟结果表明:与现有的两种技术相比,在相同的最坏延时情况下,新结构具有更好的抗噪声能力,分别提升了12%和8%;而在具有相同的抗噪声能力的情况下,新结构具有更快的速度,分别提高了1.6倍和1.4倍.     

改进结构的64位CMOS并行加法器设计与实现

介绍了一个用于高性能的微处理器和 DSP处理器的快速 6 4位二进制并行加法器 .为了提高速度 ,改进了加法器结构 ,该结构大大减少了加法器各级门的延迟时间 .基于改进的加法器结构 ,有效地使用动态复合门、时钟延迟多米诺逻辑和场效应管尺寸缩小技术 ,可以取得良好的电路性能 .该加法器采用 U MC 2 .5 V 0 .2 5μm 1层多晶 5层金属的 CMOS工艺实现 .完成一次加法运算的时间是 70 0 ps,比传统结构的加法器快 2 0 % ;面积和功耗分别是0 .16 m m2和 2 0 0 m W@5 0 0 MHz,与传统结构加法器相当 .     

High-Speed,Robust CMOS Dynamic Circuit Design

提出了一种利用窄脉冲发生器驱动输出级，以提高电路抗噪声能力，同时保持动态电路的高速特性的多输入动态逻辑电路. 提出了这种电路的分析模型，用于说明电路的抗噪声特性和管子的参数设置. 在0.18μm CMOS工艺，1.8V的Vdd电压和55℃的环境温度下，模拟结果表明：与现有的两种技术相比，在相同的最坏延时情况下，新结构具有更好的抗噪声能力，分别提升了12%和8%; 而在具有相同的抗噪声能力的情况下，新结构具有更快的速度，分别提高了1.6倍和1.4倍.