红外焦平面探测器封装结构热应力分析

红外焦平面探测器是一个主要由引线基板、硅读出电路、铟柱和探测器芯片组成的多层结构。由于材料层间热膨胀系数的差异,低温时探测器中会产生相当大的热应力,对探测器温度循环可靠性影响严重。为了考察红外焦平面探测器低温下的热应力情况,建立了探测器结构的有限元分析模型;利用该模型分析了引线基板热膨胀系数、弹性模量,及其厚度分别对Si、CdZnTe衬底类型的探测器热失配应力和形变的影响;根据对这两种类型探测器的分析结果,分别提出了相应的改进方法,并对方法进行了计算验证。     

10 μm间距红外探测器铟柱制备研究

小间距红外探测器目前已成为红外探测器技术发展的一个重要方向.用于连接探测器芯片与读出电路芯片的铟柱的制备工艺水平成为影响器件性能的一个重要因素.介绍了一种10μm间距红外探测器铟柱的制备工艺.新工艺采用多次铟柱生长结合离子刻蚀的手段,最终剥离和制备出高度为8 μm、非均匀性小于5％的10μm间距红外探测器读出电路铟柱,...     

大面阵碲镉汞芯片的耦合热应力模型与结构优化

针对大面阵碲镉汞芯片热应力仿真分析过程中计算量与准确性不能兼容的问题，通过在芯片互联区的不同位置引入小规模铟柱阵列建立了耦合热应力的优化仿真模型。借助此模型进行热应力分析，发现在铟柱的上下表面附近区域产生了较大的热应力，同时边缘及角落处的阵列单元内部所产生的热应力更大(最高达225.69 MPa)。进一步对芯片的结构进行了优化，获得了最优读出电路及碲锌镉衬底厚度。此外，仿真结果表明，单面铟是热应力较低的铟柱结构，减小铟柱的半径可以进一步减小其内部的热应力。所提出的热应力仿真优化模型为大面阵碲镉汞芯片内部的热应力分析提供了更准确有效的分析方法以及器件设计方面的理论指导。     

读出电路铟柱打底层对铟柱成球高度的影响

针对超大规模红外探测器读出电路铟柱成球后高度过低导致倒装互连难度增加这一问题,设计了试验,并分析讨论了读出电路铟柱打底层（UBM）形状对铟柱成球高度的影响。得出了铟球高度与铟柱尺寸和铟柱生长高度成正比,与读出电路铟柱打底层尺寸成反比,并提出了进一步增加铟球高度的思路。     

温度冲击下背向集成微透镜阵列红外探测器热应力分析

针对温度冲击下红外探测器芯片的高碎裂几率问题,借助ANSYS分析软件,对背向集成微透镜阵列锑化铟探测器热应力随阵列规模的演变规律、以及64×64大面阵探测器热应力及其分布进行了研究.首先针对8×8小面阵背向集成微透镜阵列锑化铟红外探测器进行热应力分析,得到芯片上最大应力值达到最小时探测器的结构参数.以此为探测器典型结构参数,使阵列规模从8×8倍增到64×64,从而在较短的时间内得到温度冲击下探测器中热应力随阵列规模的演变规律,以及64×64探测器的热应力值及其分布.结果表明:背向集成微透镜阵列锑化铟红外探测器最大应力值出现在锑化铟芯片上,并随阵列规模的增大近似呈线性增加,显示出热应力与阵列规模的相关性.在64×64红外探测器中,锑化铟芯片上表面热应力明显集中在微透镜边缘区域,铟柱阵列上表面热应力分布呈现出由外至内的环状梯度分布,而其它接触面上的热应力分布则呈现出明显的均匀性、集中性.     

混成红外探测器列阵与改善动态范围的CMOS读出电路

美国专利US7551059 (2009年6月23日授权)本发明提供一种混成图像传感器,它包括一个CMOS读出电路和一个红外探测器列阵。CMOS读出电路通过铟柱焊接与红外探测器列阵的至少一个探测器连接。CMOS读出电路包括两个放大器电路,这     

液氮冲击中InSb焦平面探测器热应力计算

液氮冲击中In Sb焦平面探测器的局部分层、局部碎裂制约着其成品率的提高。为分析液氮冲击中发生在In Sb焦平面探测器中的潜在失效模式,我们借助C.H.Hsueh提出的适用于弹性多层体系热应力计算理论,结合In Sb焦平面探测器的典型结构,忽略铟柱阵列的影响,得到了In Sb焦平面探测器中心区域热应变和热应力沿厚度方向的分布。依据热应变和热应力分布,我们认为液氮冲击中In Sb芯片和底充胶均处于拉应力状态,硅读出电路上边2/3部分处于压应力状态,下边1/3部分处于拉应力状态。整个探测器四角往上翘曲,中心区域往下凸起。这些计算结果为后续探测器组件封装中平衡复合物结构的设计提供了理论参考。     

InSb红外焦平面探测器结构应力的ANSYS分析

借助有限元软件系统分析了铟柱取不同直径时红外探测器整体结构的应力分布.模拟结果表明,在固定铟柱高度的前提下,当铟柱直径以2μm的步长从36μm减小到18μm的过程中,InSb芯片上的最大应力值呈现出先减小,后线性增加的趋势,但铟柱上应力最大值始终保持在15.7MPa左右,且分布几乎不变.S i读出电路上的应力小于InSb芯片上的应力值,变化趋势类同于InSb芯片上应力的变化趋势.铟柱直径取30μm时,InSb芯片和S i读出电路上的应力均达到最小值260MPa和140MPa,整个器件的应力分布在接触区呈现明显的集中性、均匀性,分布更合理.     

红外探测器倒装互连工艺中的铟柱高度研究北大核心CSCD

针对制冷型红外焦平面探测器倒装互连工艺中的铟柱高度展开了调研,结果显示目前行业内关于该工艺中的铟柱高度设计的离散性较大,铟柱高度范围为5~24μm,差值达到了19μm。本文构建了包含探测器芯片、铟柱、填充胶、钝化层和UBM的像元级有限元仿真模型,并根据不同的铟柱直径和高度开展了60组仿真计算,根据计算结果绘制了p-n结区最大应力值的变化曲线,并分析了应力变化规律。     

可见光对GaN基紫外焦平面读出电路的影响

GaN材料对可见光是透明的,而Si材料可以吸收可见光。在面阵GaN基紫外焦平面中,GaN探测器与Si读出电路通过铟柱倒焊互连,可见光可穿过GaN材料而被Si材料吸收。研究了可见光对于GaN基紫外焦平面读出电路影响的机制,并提出了通过在电路中覆盖铝层的方法减小可见光的影响,最后用实验证实了此方法对于抑制可见光干扰的影响的有效性。     

锑化铟红外焦平面阵列探测器的热应力结构优化

在液氮冲击实验中,锑化铟红外焦平面阵列探测器中各层材料之间线膨胀系数的不同将导致热失配产生,过大的热失配应力将引起锑化铟芯片断裂失效。为了降低热失配对锑化铟芯片的影响,基于弹性多层体系热应力计算理论,借鉴平衡复合物结构设计方法,优化平衡复合物结构上表面的热应变,使得平衡复合物结构中硅读出电路上表面的热应变尽可能接近锑化铟芯片下表面的热应变,从而大幅降低锑化铟芯片中的热应力。考虑器件加工工艺成熟度,经一系列计算表明:当硅读出电路的厚度取25 μm时,平衡复合物结构中硅读出电路上表面的热应变与InSb芯片下表面的热应变最为接近,此时锑化铟芯片中的拉应力最小。锑化铟芯片中拉应力的大幅降低,将为消减液氮冲击中锑化铟芯片的碎裂几率提供可以信赖的结构设计方案和实现途径。     

Indium bump array fabrication on small CMOS circuit for flip-chip bonding

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64×64 indium arrays with 20μm-high,30μm-diameter bumps are successfully formed on a 5×6.5 mm~2 CMOS chip.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

高斯激光辐照焦平面探测器温度场分析与仿真

为了研究激光辐照焦平面探测器的温度效应,采用ANSYS有限元软件建立高斯脉冲激光辐照锑化铟红外焦平面探测器的3维结构分析模型,并对该探测器3维温度场效应进行了研究。结果表明,激光辐照下,探测器最大温度出现在最上层的锑化铟芯片上,探测器最大温度达到锑化铟芯片熔点温度798K时,将会引起探测器的热熔融损伤,且熔融损伤阈值受到脉宽、光斑半径等激光参量的影响;高斯脉冲激光辐照下,探测器中各层材料的温度场分布呈现出非连续的高温极值区域,其主要原因是位于锑化铟红外焦平面探测器中间层相间分布的铟柱和底充胶具有迥异的热学性质,并且造成探测器温度场云图中锑化铟芯片、底充胶与硅读出电路高温极值区域形成类似于互补的高温分布。这为进一步研究温升效应引起的应力场分布、提高探测器激光防护性能提供了重要的理论分析依据。     

Thermal cycling lifetime of flip chip on board circuits with solder bumps and isotropically conductive adhesive joints

Flip chip on board (FCOB) circuits with solder bumps or isotropically conductive adhesives (ICA) may be subject to joint failure during thermal cycling. Although use of epoxy underfill can increase the lifetime significantly, there is still a risk of failure if the material properties of the underfill material are not adequate to prevent excessive values of stress and strain in the joints. This paper presents experimental measurements of the number of thermal cycles to failure for both solder reflow and ICA joint FCOB circuits. Measurements have been carried out for several different material systems with various types of underfill. The measurements of solder bump lifetime are compared to a lifetime model based on analytical calculations of solder strain. For an underfill type without filler (CTE=58 ppm//spl deg/C), the measurements are in excellent agreement with the model predictions, both giving an average lifetime of around 1500 thermal cycles between -55 and 125/spl deg/C. For two filled types of underfill with CTE nearly matched to that of solder, the measured average lifetimes vary from around 2700 to 5500 cycles. The corresponding model predictions are around 6000 and 7000 cycles, respectively. Measurements of the lifetime of FCOB's with ICA connections have been carried out for two different material systems. The obtained lifetimes vary between approximately 500 and 4000 cycles. No systematic lifetime variation with the thermal expansion of the underfill has been observed, but the lifetime seems to be dependent on the properties of the bump on the chip pad. Delamination, for instance at the ICA/bump interface, is found to be an important cause of failure.     

红外探测器倒装互连技术进展

随着红外焦平面技术的发展,红外探测器探测波段已由单波段变为双色及四色波段,半导体元件的封装数量由最初的数十个发展到数百万个,I/O输出密度不断增大,传统微互联技术如引线键合技术、载带自动焊技术等已根本无法满足器件要求。倒装焊技术以其封装尺寸小、互联密度高、生产成本低的特点越来越受到人们的亲睐。倒装互连工艺主要包括:UBM 制备、铟膜沉积、回流成球、倒压焊、填充背底胶。介绍了各工艺步骤的发展状况,并对铟膜沉积、铟柱增高工艺进行详细阐述。     

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.