氮化H2-O2合成薄栅氧抗辐照特性

对氮化H2-O2合成薄栅氧抗辐照性能进行了研究,将H2-O2合成和氮氧化栅两种技术结合起来,充分利用两者的优点制成三层结构的Sandwich栅,对比常规氧化、H2-O2合成氧化和氮化H2-O2合成氧化三种方式及不同退火条件,得出氮化H2-O2合成氧化方法抗辐照性能最佳,采用硅化物工艺加快速热退火是未来抗辐照工艺发展的趋势;并对氮化H2-O2合成栅的抗辐照机理进行了研究.     

全耗尽CMOS/SOI工艺

对全耗尽 CMOS/ SOI工艺进行了研究 ,成功地开发出成套全耗尽 CMOS/ SOI抗辐照工艺 .其关键工艺技术包括 :氮化 H2 - O2 合成薄栅氧、双栅和注 Ge硅化物等技术 .经过工艺投片 ,获得性能良好的抗辐照 CMOS/ SOI器件和电路 (包括 10 1级环振、2 0 0 0门门海阵列等 ) ,其中 ,n MOS:Vt=0 .7V,Vds=4 .5～ 5 .2 V,μeff=4 6 5 cm2 / (V· s) ,p MOS:Vt=- 0 .8V ,Vds=- 5～ - 6 .3V,μeff=2 6 4 cm2 / (V· s) .当工作电压为 5 V时 ,0 .8μm环振单级延迟为 4 5 ps     

氮化H2-O2合成薄栅介质的击穿特性

研究了14～16nm的H2-O2合成薄栅介质击穿特性.实验发现,N2O气氛氮化H2-O2合成法制备的薄栅介质能够有效地提高栅介质的零时间击穿特性.H2-O2合成法制备的样品,其击穿场强分布特性随测试MOS电容面积的增加而变差,而氮化H2-O2合成薄栅介质的击穿特性随测试MOS电容面积的增加基本保持不变.对于时变击穿,氮化同样能够明显提高栅介质的击穿电荷及其分布.     

氮化H2-O2合成薄栅介质的击穿特性

研究了14～16nm的H2-O2合成薄栅介质击穿特性.实验发现,N2O气氛氮化H2-O2合成法制备的薄栅介质能够有效地提高栅介质的零时间击穿特性.H2-O2合成法制备的样品,其击穿场强分布特性随测试MOS电容面积的增加而变差,而氮化H2-O2合成薄栅介质的击穿特性随测试MOS电容面积的增加基本保持不变.对于时变击穿,氮化同样能够明显提高栅介质的击穿电荷及其分布.     

多晶硅后热退火引起SiO_2栅介质可靠性下降的原因分析及其抑制方法

实验研究表明 ,多晶硅后的高温退火明显引起热 Si O2 栅介质击穿电荷降低和 FN应力下电子陷阱产生速率增加 .采用 N2 O氮化则可完全消除这些退化效应 ,而且氮化栅介质性能随着退火时间增加反而提高 .分析认为 ,高温退火促使多晶硅内 H扩散到 Si O2 内同 Si— O应力键反应形成 Si— H是多晶硅后 Si O2 栅介质可靠性退化的主要原因 ;氮化抑制退化效应是由于 N “缝合”了 Si O2 体内的 Si— O应力键缺陷 .     

全耗尽CMOS/SOI工艺

对全耗尽CMOS/SOI工艺进行了研究,成功地开发出成套全耗尽 CMOS/SOI抗辐照工艺.其关键工艺技术包括:氮化H2-O2合成薄栅氧、双栅和注Ge硅化物等技术.经过工艺投片,获得性能良好的抗辐照CMOS/SOI器件和电路(包括101级环振、2000门门海阵列等),其中,nMOS:Vt=0.7V,Vds=4.5～5.2V,μeff=465cm2/(V*s),pMOS:Vt=-0.8V,Vds=-5～-6.3V,μeff=264cm2/(V*s).当工作电压为5V时,0.8μm环振单级延迟为45ps.     

多晶硅后热退火引起SiO2栅介质可靠性下降的原因分析及其抑制方法

实验研究表明,多晶硅后的高温退火明显引起热SiO2栅介质击穿电荷降低和FN应力下电子陷阱产生速率增加．采用N2O氮化则可完全消除这些退化效应,而且氮化栅介质性能随着退火时间增加反而提高．分析认为,高温退火促使多晶硅内H扩散到SiO2内同Si—O应力键反应形成Si—H是多晶硅后SiO2栅介质可靠性退化的主要原因;氮化抑制退化效应是由于N“缝合”了SiO2体内的Si—O应力键缺陷．     

离子注入氮化薄SiO_2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化 10 nm薄栅 Si O2 的特性 .实验证明氮化后的薄 Si O2 栅具有明显的抗硼穿透能力 ,它在 FN应力下的氧化物陷阱电荷产生速率和正向 FN应力下的慢态产生速率比常规栅介质均有显著下降 ,氮化栅介质的击穿电荷 (Qbd)比常规栅介质提高了 2 0 % .栅介质性能改善的可能原因是由于离子注入工艺在栅 Si O2 中引进的 N+离子形成了更稳定的键所致     

一种抗总剂量辐照的NMOSFETs

在商用 SIMOX衬底上制备了抗辐照 NMOSFETs,使用的主要技术手段有 :氮化 H2 -O2 合成栅介质加固正栅 ;增加体区掺杂 ,以提高背栅阈值电压 ;采用 C型体接触结构 ,消除边缘寄生晶体管。结果表明 ,在经受 1× 1 0 6 rad( Si)的辐照后 ,器件特性没有明显恶化     

O2+CHCCl3氧化对6H-SiC MOS电容界面特性的改善

采用新颖的干O2 CHCCl3(TCE)氧化工艺，制备了P型和N型6H—SiCMOS电容器，并与常规热氧化工艺以及氧化加NO退火工艺进行了对比实验。结果表明，O2 TCE氧化不仅提高了氧化速率，而且降低了界面态密度和氧化层有效电荷密度，提高了器件可靠性。可以预测，O2 TCE氧化与湿NO退火相结合的工艺是一种有前途的制备高沟道迁移率、高可靠性SiCMOS—FET的栅介质工艺。     

Effect of capping silicon nitride layer and nitrided gate oxide on hump of transistors

In this letter, we investigate the effect of capping silicon nitride and nitrided gate oxide on the hump in the sub-threshold slope of various transistors. Silicon wafers having both high- and low-voltage transistors are fabricated. The thin gate oxide is grown by nitric oxidation, while two step process of dry oxidation and low-pressure chemical vapor deposition (LPCVD) is used for the thick gate oxide. Note that the thickness of thin gate oxide is 4.5 nm, and 29 nm for thick gate oxide. It appears that both low-voltage nMOS and pMOS do not show any hump, nor does high-voltage pMOS. The subthreshold hump of high-voltage nMOS depends on process conditions. It shows severe hump without capping silicon nitride layer due to moisture diffusion during thermal anneal after interlayer oxide deposition by LPCVD. It also appears that nitrided oxide is effective to prevent hump by stopping moisture diffusion.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

HCl氧化物MOS结构质子辐照诱导的界面陷阱效应

用微分电容法研究质子辐照HCl氧化物铝栅MOS结构诱导的界面陷阱,栅氧化层在1 160℃很干燥的、含0～10％HCl的气氛中热生长而成,质子辐照能量为120～300keV,注入总剂量范围为8×10~(13)～1×10~(16)p/cm~2。结果表明,辐照诱导的界面陷阱能级密度随质子能量、剂量增加而增加。然而,氧化层中掺入6％HCl时,辐照诱导的界面陷阱明显减少。这样,已能有效地改变MOS器件的抗辐照性能。实验结果可用H~+二级过程解释。     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N+注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.     

Thin gate and analog capacitor dielectrics for submicron device fabrication

The miniaturization of devices in ULSI circuits are accompanied by shrinking vertical, as well as horizontal, device parameters such as junction depth, lateral impurity diffusion and film thicknesses. This is achieved by decoupling process steps,i.e. processing at a reduced thermal budget. However, as device dimensions decrease, greater demand in transistor noise immunity and reliability may not be achievable with low-temperature (<900° C) oxidation processes. Low temperature CVD ONO (oxide-nitride-oxide) dielectrics have been evaluated for applications in ULSI gate as well as capacitor structures. Time dependent dielectric breakdown data have shown that ONO has longer lifetime than thermal oxide of equivalent thickness. Such stacked dielectrics nevertheless result in complex processing steps. With the advances in rapid thermal processing equipment today, rapid thermal oxide (RTO) has been shown to offer potential benefits of high temperature without significant addition to the overall thermal budget. We have shown that transistors with RTO gate oxides exhibit longer lifetime and lower noise compared to those with furnace grown gate oxides. We have also shown that interpoly RTO oxides have remarkable dielectric strength of >8 MV/cm. For enhanced radiation hardness and impurity masking capability as well as higher permittivity, rapid thermal nitrided oxides may be a potential choice deserving further evaluation. These nitrided oxides must be reoxidized to reduce densities of interface states and electron traps created during the nitridation process.     

SOI抗总剂量辐射加固工艺栅氧可靠性研究

文章对采用了埋层二氧化硅抗总剂量加固工艺技术的SOI器件栅氧可靠性进行研究,比较了干法氧化和湿法氧化工艺的栅氧击穿电荷,干法氧化的栅氧质量劣于湿法氧化。采用更敏感的12.5nm干法氧化栅氧工艺条件,对比采用抗总剂量辐射加固工艺前后的栅氧可靠性。抗总剂量辐射加固工艺降低了栅氧的击穿电压和击穿时间。最后通过恒压法表征加固工艺的栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5nm栅氧在常温5.5V工作电压下TDDB寿命远大于10年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。     

栅氧化方式对N沟输入CMOS运算放大器电离辐射效应的影响

介绍了干氧和氢氧合成两种不同栅氧化方式下制作的N沟输入CMOS运算放大器电路的电离辐照响应特征.并通过对电路内部单管特性损伤分析的比较,探讨了引起两者辐照敏感性差异的原因.结果显示,氢氧合成工艺比干氧工艺损伤明显的原因,是因为H的引入产生了更多的界面态,从而使其单管的跨导明显下降所致.这表明,抑制辐照感生氧化物电荷尤其是界面态的增长,对提高电路的抗辐射特性至关重要.     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Anodic oxide gate a-Si:H MOSFET

The first a-Si:H MOSFET having native oxide at the insulator/a-Si:H interface is reported. Anodic oxidation in the AGW electrolyte is applied to Al/a-Si:H structures to form Al2O3/native oxide/a-Si:H gate structures. Resulting FETs show typical effective mobilities of 0.02 cm2/V s after proper low-temperature annealing in H2. Anodic oxidation is thus proved to be applicable to a-Si:H device technology as a low-temperature oxidation process.     

Hot-carrier degradation of LDD MOSFET's with gate oxynitride grownin N2O

Hot carrier immunity (HCI) of single drain (SD) and lightly doped drain (LDD) n-MOSFET's with gate oxide and N₂O gate oxynitride was compared. Gate oxynitride shows better HCI than gate oxide in SD devices but comparable in LDD devices. We show that oxide grown during the poly-silicon oxidation process after gate poly-silicon definition plays an important role in determining the hot carrier resistance of LDD n-MOSFET's with N₂O gate oxynitride