应用于生物医疗的0.6-V 8.3-ENOB 异步时序逐次逼近型模数转换器

A microwatt asynchronous successive approximation register （SAR） analog-to-digital converter （ADC） is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power require- ments of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.     

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm².     

一种应用于能量攫取系统的低功耗的工作于亚阈值区域的基准电压源的设计

We propose a bandgap reference, which works in sub-threshold regions to the reduce power consumption in applications such as those in energy harvesting systems that stimulate the development of power management for low power consumption applications.Measurements shows that the supply current of the proposed bandgap reference is only 6.87 μA, including a voltage buffer consuming 3.6 μA of supply current, when the supply voltage is 5 V.The supply voltage can vary from 3 to 11 V and the line regulation of the proposed bandgap reference output voltage is 0.875 mV/V at room temperature.The temperature coefficiency is 88.9 ppm from 10 to 100° C when the supply voltage is 5 V.     

50 MHz dual-mode buck DC-DC converter

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS (BIAS current). A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18 μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.     

A Dual-Mode Step-up DC/DC Converter IC with Current-Limiting and EMI Reduction Techniques

This paper presents a novel dual-mode step-up （boost） DC/DC converter. Pulse-frequency modulation （PFM） is used to improve the efficiency at light load. This converter can operate between pulse-width modulation （PWM） and pulse-frequency modulation. The converter will operate in PFM mode at light load and in PWM mode at heavy load. The maximum conversion efficiency of this converter is 96%. The conversion efficiency is greatly improved when load current is below 100 mA. Additionally, a soft-start circuit and a variable-sawtooth frequency circuit are proposed in this paper. The former is used to avoid the large switching current at the start up of the converter and the latter is utilized to reduce the EMI of the converter.     

Energy Efficiency Optimization in Relay-Assisted Networks with Energy Harvesting Relay Constraints

In this paper we consider data transmission in a decode-and-forward(DF)relay-assisted network in which the relay is energy harvesting(EH) powered while the base station(BS) is power-grid powered.Our purpose is to maximize the BS’s energy efficiency(EE) while making full use of the relay’s renewable energy and satisfying the specific average throughput requirements.In contrast to existing literature on energy harvesting system which only considers the radio transmission power,we take the static circuit power into account as well.We formulate the EE optimization problem and prove that the EE of the BS and relay are both quasiconvex in the instantaneous transmission rate.Then we divide the complex optimization problem into two point-to-point link level optimization parts and propose an energyefficient resource allocation(EERA) scheme in which power control and sleep mode management are jointly used.The simulation results demonstrate that EERA may achieve good energy saving effects.We also compare the EE of an energy harvesting relay system with a power-grid powered one and provide more insight into the EE problem of energy harvesting relay system.     

A self-powered piezoelectric energy harvesting interface circuit with efficiency-enhanced P-SSHI rectifier

The key to self-powered technique is initiative to harvest energy from the surrounding environment.Harvesting energy from an ambient vibration source utilizing piezoelectrics emerged as a popular method.Efficient interface circuits become the main limitations of existing energy harvesting techniques.In this paper,an interface circuit for piezoelectric energy harvesting is presented.An active full bridge rectifier is adopted to improve the power efficiency by reducing the conduction loss on the rectifying path.A parallel synchronized switch harvesting on inductor (P-SSHI) technique is used to improve the power extraction capability from piezoelectric harvester,thereby trying to reach the theoretical maximum output power.An intermittent power management unit (IPMU) and an output capacitor-less low drop regulator (LDO) are also introduced.Active diodes (AD) instead of traditional passive ones are used to reduce the voltage loss over the rectifier,which results in a good power efficiency.The IPMU with hysteresis comparator ensures the interface circuit has a large transient output power by limiting the output voltage ranges from 2.2 to 2 V.The design is fabricated in a SMIC 0.18μm CMOS technology.Simulation results show that the flipping efficiency of the P-SSHI circuit is over 80％ with an off-chip inductor value of 820 μH.The output power the proposed rectifier can obtain is 44.4μW,which is 6.7× improvement compared to the maximum output power of a traditional rectifier.Both the active diodes and the P-SSHI help to improve the output power of the proposed rectifier.LDO outputs a voltage of 1.8 V with the maximum 90％ power efficiency.The proposed P-SSHI rectifier interface circuit can be self-powered without the need for additional power supply.     

一种带双重纹波补偿的10MHZ导通时间纹波控制降压型转化器

A 10 MHz ripple-based on-time controlled buck converter is presented.A novel low-cost dual ripple compensation,which consists of coupling capacitor compensation and passive equivalent series resistance compensation, is proposed to achieve a fast load transient response and robust stability simultaneously.Implemented in a 2P4M 0.35μm CMOS process,the converter achieves fix-frequency output with a ripple of below 10 mV and an overshoot of 10 mV at 400 mA step load transient response.With width optimization of the power transistors in an ultra-heavy load and PFM control in a light load,the efficiency stays at over 83%for a load range from 20 mA to 1.5 A and the peak efficiency reaches 90.16%.     

8位12MS/s带片上参考电压的异步逐次逼近模数转换器

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers.A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity.Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm.An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype,fabricated in UMC 0.18μm CMOS technology,achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s.The total power consumption is 0.918 mW for a 1.8 V supply,while the onchip reference consumes 53%of the total power.It achieves a figure of merit of 180 fJ/conv-step,excluding the reference’s power consumption.     

A 1500 mA,10 MHz on-time controlled buck converter with ripple compensation and efficiency optimization

正A 1500 mA,10 MHz self-adaptive on-time(SOT) controlled buck DC-DC converter is presented.Both a low-cost ripple compensation scheme(RCS) and a self-adaptive on-time generator(SAOTG) are proposed to solve the system stability and frequency variation problem.Meanwhile a self-adaptive power transistor sizing(SAPTS) technique is used to optimize the efficiency especially with a heavy load.The circuit is implemented in a 2P4M 0.35μm CMOS process.A small external inductor of 0.47μH and a capacitor of 4.7μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV.The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling(DVS) performance is a rise of 16μs/V and a fall of 20μs/V.With a SAPTS technique and PFM control,the efficiency is maintained at more than 81%for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.     

一种用于数字控制DC-DC转换器的近似时间最优轨迹预测法

The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.     

一种平均电流模式控制的单电感双输出型开关电源转换器

An integrated single-inductor dual-output （SIDO） switching DC-DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.     

Survivable Virtual Network Mapping Using Optimal Backup Topology in Virtualized SDN

Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping approach using optimal backup topology to survive a single link failure with less resource consumption. Firstly, according to whether the path splitting is supported by virtual networks, we propose the OBT-I and OBT-II algorithms respectively to generate an optimal backup topology which minimizes the total amount of bandwidth constraints. Secondly, we propose a Virtual Network Mapping algorithm with coordinated Primary and Backup Topology （VNM-PBT） to make the best of the substrate network resource. The simulation experiments show that our proposed approach can reduce the average resource consumption and execution time cost, while improving the request acceptance ratio of VNs.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.     

应用于低中频和零中频DVB调谐器中8阶信道滤波器设计

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.