A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/℃ in the temperature range of -40 to 120 ℃, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.     

多管组合曲率补偿低压带隙基准源

A new bandgap reference(BGR) curvature compensation technology is proposed,which is a kind of multiple transistor combination.On the basis of the existing first-order bandgap reference technology,a compensation current circuit consisting of a sink current branch and a source current branch is added.The BGR was designed and simulated by using Semiconductor Manufacturing International Corporation(SMIC) 0.18μm CMOS process.The simulation results showed that when the power supply voltage was 1 V,the temperature coefficient of the BGR was 2.08 ppm/℃with the temperature range from—40 to 125℃,the power supply rejection ratio (PSRR) was—64.77 dB and the linear regulation was 0.44 mV/V with the supply power changing from 0.85 to 1.8 V.     

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.     

一种带热滞回保护的高精度高电源抑制比带隙基准源

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μ m 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm². Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from –40 to 150 ℃, the power supply rejection ratio is –98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.     

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm².     

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage.     

一种连续输出的小失调开关电容带隙基准源

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.     

An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology

A novel Power-on-reset （POR） circuit is proposed with ultra-low steady-state current consumption. A band=gap voltage eomparator is used to generate a stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted to cut the supply of band-gap voltage comparator, which gained ultra-low current consumption in steady-state after the POR rest process completed. The state of POR circuit is maintained through a state latch circuit. The whole cir- cuit was designed and implemented in 65rim C1V[OS tech- nology with an active area of 120ttm＊160~m. Experimental results show that it has a steady pull=up voltage of 0.69V and a brown-out voltage of 0.49V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only 9hA. The proposed circuit is suitable to be integrated in system on chip to provide a reliable POR signal.     

一种新型全集成高速双模分频器

A fully integrated 2n/2n+1 dual-modulus divider in GHz frequency range is presented.The improved structure can make all separated logic gates embed into correlative D flip–flops completely.In this way,the complex logic functions can be performed with a minimum number of devices and with maximum speed,so that lower power consumption and faster speed are obtained.In addition,the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output.According to the design demand,the circuit is fabricated in 0.18 m standard CMOS process,and the measured results show that its operating frequency range is 1.1–2.5 GHz.The dual-modulus divider dissipates 1.1 m A from a 1.8 V power supply.The temperature coefficient of the reference voltage circuit is 8.3 ppm/°C when the temperature varies from40 to C125°C.By comparison,the dual-modulus divide designed in this paper can possess better performance and flexibility.     

应用于碲锌镉探测器逐次逼近模数转换器基准电压的研究

An on-chip reference voltage has been designed in capacitor-resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μ m 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80℃, the temperature coefficient is 12.2 ppm/℃. The PSRR was-70 dB@100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449×614 μm². The total power consumption is only 1.092 mW.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

应用于低中频和零中频DVB调谐器中8阶信道滤波器设计

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.     

Survivable Virtual Network Mapping Using Optimal Backup Topology in Virtualized SDN

Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping approach using optimal backup topology to survive a single link failure with less resource consumption. Firstly, according to whether the path splitting is supported by virtual networks, we propose the OBT-I and OBT-II algorithms respectively to generate an optimal backup topology which minimizes the total amount of bandwidth constraints. Secondly, we propose a Virtual Network Mapping algorithm with coordinated Primary and Backup Topology （VNM-PBT） to make the best of the substrate network resource. The simulation experiments show that our proposed approach can reduce the average resource consumption and execution time cost, while improving the request acceptance ratio of VNs.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

具有频率调谐的GNSS接收机双模复数滤波器

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A K-Median Facility Location Agent for Low-Cost Service Selection in Digital Community Network

With the increasing number of web services, it becomes a difficult task for an ordinary user to select an appropriate service. Hence, it is conventional that users in a digital community network take part in a collaborative mechanism for the purpose of service selection. The participation usually brings unnecessary burdens for users, such as giving opinions, storing service information. Extra communication overhead hinders the performance of the network. Thus, the community administrators are facing a problem of how to obtain an overall service selection result for the whole community readily and effectively. To address this problem, we present a k-median facility location agent model. The model analyzes the procedure of service selection through five entities and six types of messages. Two algorithms are elaborated in pursuit of a global optimization concerning connection costs between users and facilities where services are deployed. To evaluate our model, we conduct extensive simulations and present a detailed analysis of the simulation results.